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authorAdam Izraelevitz2018-03-21 14:24:25 -0700
committerGitHub2018-03-21 14:24:25 -0700
commit6ea4ac666e4ce8dfaca1545660f372fccff610f5 (patch)
tree8f2125855557962d642386fe8b49ed0396f562c2 /src/main/scala/firrtl/passes
parent6b195e4a5348eed2e714e1183024588c5f91a283 (diff)
GroupModule Transform (#766)
* Added grouping pass * Added InfoMagnet and infomappers * Changed return type of execute to allow final CircuitState inspection * Updated dedup. Now is name-agnostic * Added GroupAndDedup transform
Diffstat (limited to 'src/main/scala/firrtl/passes')
-rw-r--r--src/main/scala/firrtl/passes/memlib/MemIR.scala1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/main/scala/firrtl/passes/memlib/MemIR.scala b/src/main/scala/firrtl/passes/memlib/MemIR.scala
index 54441481..5fb837c1 100644
--- a/src/main/scala/firrtl/passes/memlib/MemIR.scala
+++ b/src/main/scala/firrtl/passes/memlib/MemIR.scala
@@ -30,4 +30,5 @@ case class DefAnnotatedMemory(
def toMem = DefMemory(info, name, dataType, depth,
writeLatency, readLatency, readers, writers,
readwriters, readUnderWrite)
+ def mapInfo(f: Info => Info): Statement = this.copy(info = f(info))
}