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| author | Jim Lawson | 2018-02-16 17:10:30 -0800 |
|---|---|---|
| committer | GitHub | 2018-02-16 17:10:30 -0800 |
| commit | edcb81a34dbf8a04d0b011aa1ca07c6e19598f23 (patch) | |
| tree | aba2e3b8b921f9fdc861ed51687735f6d18d7bff /src/main/scala/firrtl/passes/clocklist | |
| parent | 74a3b302df4422bec47e754cad1703b36ff75cd2 (diff) | |
Replacematcherror - catch exceptions and convert to internal error. (#424)
* Catch exceptions and convert to internal error.
We need to update the displayed message to incorporate a line number and text to be used for the issue.
* Cleanup exception handling/throwing.
Re-throw expected (or uncorrectable exceptions).
Provide Utils.getThrowable() to get the first (eldest) or last throwable in the chain.
Update tests to conform to FreeSpec protocol.
* Minor cleanup
Admit we've updated some deprecated ScalaTest methods.
Diffstat (limited to 'src/main/scala/firrtl/passes/clocklist')
| -rw-r--r-- | src/main/scala/firrtl/passes/clocklist/ClockList.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/scala/firrtl/passes/clocklist/ClockList.scala b/src/main/scala/firrtl/passes/clocklist/ClockList.scala index 073eb050..be4d99fc 100644 --- a/src/main/scala/firrtl/passes/clocklist/ClockList.scala +++ b/src/main/scala/firrtl/passes/clocklist/ClockList.scala @@ -44,7 +44,7 @@ class ClockList(top: String, writer: Writer) extends Pass { val modulesToInline = (c.modules.collect { case Module(_, n, _, _) if n != top => ModuleName(n, CircuitName(c.main)) }).toSet val inlineTransform = new InlineInstances val inlinedCircuit = inlineTransform.run(onlyClockCircuit, modulesToInline, Set(), None).circuit - val topModule = inlinedCircuit.modules.find(_.name == top).getOrElse(throwInternalError) + val topModule = inlinedCircuit.modules.find(_.name == top).getOrElse(throwInternalError(Some("no top module"))) // Build a hashmap of connections to use for getOrigins val connects = getConnects(topModule) |
