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authorAdam Izraelevitz2017-03-23 16:16:24 -0700
committerGitHub2017-03-23 16:16:24 -0700
commit67eb4e2de6166b8f1eb5190215640117b82e8c48 (patch)
tree18cbaf901eff58262d833bf5bc0d75262c9ab57d /src/main/scala/firrtl/passes/clocklist
parent4cffd184397905eeb79e2df0913b4ded97dc8558 (diff)
Pass now subclasses Transform (#477)
Diffstat (limited to 'src/main/scala/firrtl/passes/clocklist')
-rw-r--r--src/main/scala/firrtl/passes/clocklist/ClockList.scala1
-rw-r--r--src/main/scala/firrtl/passes/clocklist/RemoveAllButClocks.scala1
2 files changed, 0 insertions, 2 deletions
diff --git a/src/main/scala/firrtl/passes/clocklist/ClockList.scala b/src/main/scala/firrtl/passes/clocklist/ClockList.scala
index 66139c49..bd2536ab 100644
--- a/src/main/scala/firrtl/passes/clocklist/ClockList.scala
+++ b/src/main/scala/firrtl/passes/clocklist/ClockList.scala
@@ -20,7 +20,6 @@ import Mappers._
* Write the result to writer.
*/
class ClockList(top: String, writer: Writer) extends Pass {
- def name = this.getClass.getSimpleName
def run(c: Circuit): Circuit = {
// Build useful datastructures
val childrenMap = getChildrenMap(c)
diff --git a/src/main/scala/firrtl/passes/clocklist/RemoveAllButClocks.scala b/src/main/scala/firrtl/passes/clocklist/RemoveAllButClocks.scala
index feb7f42e..53787b1d 100644
--- a/src/main/scala/firrtl/passes/clocklist/RemoveAllButClocks.scala
+++ b/src/main/scala/firrtl/passes/clocklist/RemoveAllButClocks.scala
@@ -20,7 +20,6 @@ import Mappers._
* expressions do not relate to ground types.
*/
object RemoveAllButClocks extends Pass {
- def name = this.getClass.getSimpleName
def onStmt(s: Statement): Statement = (s map onStmt) match {
case DefWire(i, n, ClockType) => s
case DefNode(i, n, value) if value.tpe == ClockType => s