diff options
| author | Schuyler Eldridge | 2018-08-22 16:39:07 -0400 |
|---|---|---|
| committer | Schuyler Eldridge | 2018-11-07 13:49:16 -0500 |
| commit | 61ab5a323da77dd03a24cfda3948830c3bb286c9 (patch) | |
| tree | 2ca1c57d67c571b1a414849c9c55aac4d44d44fd /src/main/scala/firrtl/passes/clocklist | |
| parent | 17b4e9835bd95dcf91c5ea5a4d7c52280031ea93 (diff) | |
Add FirrtlOptions
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Diffstat (limited to 'src/main/scala/firrtl/passes/clocklist')
| -rw-r--r-- | src/main/scala/firrtl/passes/clocklist/ClockListTransform.scala | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/main/scala/firrtl/passes/clocklist/ClockListTransform.scala b/src/main/scala/firrtl/passes/clocklist/ClockListTransform.scala index 6c7b2e18..6b265239 100644 --- a/src/main/scala/firrtl/passes/clocklist/ClockListTransform.scala +++ b/src/main/scala/firrtl/passes/clocklist/ClockListTransform.scala @@ -14,6 +14,9 @@ import Utils._ import memlib.AnalysisUtils._ import memlib._ import Mappers._ +import firrtl.options.RegisteredTransform +import scopt.OptionParser +import firrtl.stage.RunFirrtlTransformAnnotation case class ClockListAnnotation(target: ModuleName, outputConfig: String) extends SingleTargetAnnotation[ModuleName] { |