All of src/ formatted with scalafmt

1 files changed, 11 insertions, 11 deletions

diff --git a/src/main/scala/firrtl/passes/RemoveValidIf.scala b/src/main/scala/firrtl/passes/RemoveValidIf.scala
index 895cb10f..7e82b37b 100644
--- a/src/main/scala/firrtl/passes/RemoveValidIf.scala
+++ b/src/main/scala/firrtl/passes/RemoveValidIf.scala
@@ -26,14 +26,13 @@ object RemoveValidIf extends Pass {
     case ClockType => ClockZero
     case _: FixedType => FixedZero
     case AsyncResetType => AsyncZero
-    case other => throwInternalError(s"Unexpected type $other")
+    case other          => throwInternalError(s"Unexpected type $other")
   }
 
   override def prerequisites = firrtl.stage.Forms.LowForm
 
   override def optionalPrerequisiteOf =
-    Seq( Dependency[SystemVerilogEmitter],
-         Dependency[VerilogEmitter] )
+    Seq(Dependency[SystemVerilogEmitter], Dependency[VerilogEmitter])
 
   override def invalidates(a: Transform): Boolean = a match {
     case Legalize | _: firrtl.transforms.ConstantPropagation => true
@@ -42,24 +41,25 @@ object RemoveValidIf extends Pass {
 
   // Recursive. Removes ValidIfs
   private def onExp(e: Expression): Expression = {
-    e map onExp match {
+    e.map(onExp) match {
       case ValidIf(_, value, _) => value
-      case x => x
+      case x                    => x
     }
   }
 
   // Recursive. Replaces IsInvalid with connecting zero
-  private def onStmt(s: Statement): Statement = s map onStmt map onExp match {
-    case invalid @ IsInvalid(info, loc) => loc.tpe match {
-      case _: AnalogType => EmptyStmt
-      case tpe => Connect(info, loc, getGroundZero(tpe))
-    }
+  private def onStmt(s: Statement): Statement = s.map(onStmt).map(onExp) match {
+    case invalid @ IsInvalid(info, loc) =>
+      loc.tpe match {
+        case _: AnalogType => EmptyStmt
+        case tpe => Connect(info, loc, getGroundZero(tpe))
+      }
     case other => other
   }
 
   private def onModule(m: DefModule): DefModule = {
     m match {
-      case m: Module => Module(m.info, m.name, m.ports, onStmt(m.body))
+      case m: Module    => Module(m.info, m.name, m.ports, onStmt(m.body))
       case m: ExtModule => m
     }
   }