Added Expand Whens pass

1 files changed, 205 insertions, 6 deletions

diff --git a/src/main/scala/firrtl/passes/Passes.scala b/src/main/scala/firrtl/passes/Passes.scala
index 591f4c99..7cd4fdcf 100644
--- a/src/main/scala/firrtl/passes/Passes.scala
+++ b/src/main/scala/firrtl/passes/Passes.scala
@@ -31,7 +31,7 @@ trait StanzaPass extends LazyLogging {
     val fromStanza = Files.createTempFile(Paths.get(""), n, ".fir")
     Files.write(toStanza, c.serialize.getBytes)
 
-    val cmd = Seq("firrtl-stanza", "-i", toStanza.toString, "-o", fromStanza.toString, "-b", "firrtl") ++ 
+    val cmd = Seq("firrtl-stanza", "-i", toStanza.toString, "-o", fromStanza.toString, "-b", "firrtl", "-p", "c") ++ 
               stanzaPasses.flatMap(x=>Seq("-x", x))
     logger.debug(cmd.mkString(" "))
     val ret = cmd.!
@@ -44,12 +44,18 @@ trait StanzaPass extends LazyLogging {
 }
 
 object PassUtils extends LazyLogging {
-  val listOfPasses: Seq[Pass] = Seq(ToWorkingIR,ResolveKinds,ResolveGenders,PullMuxes,ExpandConnects,RemoveAccesses)
+  val listOfPasses: Seq[Pass] = Seq(ToWorkingIR,ResolveKinds,ResolveGenders,PullMuxes,ExpandConnects,RemoveAccesses,ExpandWhens)
   lazy val mapNameToPass: Map[String, Pass] = listOfPasses.map(p => p.name -> p).toMap
 
-  def executePasses(c: Circuit, passes: Seq[Pass]): Circuit = {
+  def executePasses(c: Circuit, passes: Seq[Pass]): Circuit = { 
     if (passes.isEmpty) c
-    else executePasses(passes.head.run(c), passes.tail)
+    else {
+       val p = passes.head
+       val name = p.name
+       logger.debug(c.serialize())
+       logger.debug(s"Starting ${name}")
+       executePasses(p.run(c), passes.tail)
+    }
   }
 }
 
@@ -623,8 +629,201 @@ object RemoveAccesses extends Pass {
 }
 
 object ExpandWhens extends Pass with StanzaPass {
-  def name = "Expand Whens"
-  def run (c:Circuit): Circuit = stanzaPass(c, "expand-whens")
+   def name = "Expand Whens"
+   var mname = ""
+// ; ========== Expand When Utilz ==========
+   def add (hash:HashMap[WrappedExpression,Expression],key:WrappedExpression,value:Expression) = {
+      hash += (key -> value)
+   }
+
+   def get_entries (hash:HashMap[WrappedExpression,Expression],exps:Seq[Expression]) : HashMap[WrappedExpression,Expression] = {
+      val hashx = HashMap[WrappedExpression,Expression]()
+      exps.foreach { e => {
+         val value = hash.get(e)
+         value match {
+            case (value:Some[Expression]) => add(hashx,e,value.get)
+            case (None) => {}
+         }
+      }}
+      hashx
+   }
+   def get_female_refs (n:String,t:Type,g:Gender) : Seq[Expression] = {
+      val exps = create_exps(WRef(n,t,ExpKind(),g))
+      val expsx = ArrayBuffer[Expression]()
+      def get_gender (t:Type, i:Int, g:Gender) : Gender = {
+         val f = get_flip(t,i,DEFAULT)
+         times(g, f)
+      }
+      for (i <- 0 until exps.size) {
+         get_gender(t,i,g) match {
+            case BIGENDER => expsx += exps(i)
+            case FEMALE => expsx += exps(i)
+            case _ => false
+         }
+      }
+      expsx
+   }
+   
+   // ------------ Pass -------------------
+   def run (c:Circuit): Circuit = {
+      def void_all (m:InModule) : InModule = {
+         mname = m.name
+         def void_all_s (s:Stmt) : Stmt = {
+            (s) match {
+               case (_:DefWire|_:DefRegister|_:WDefInstance|_:DefMemory) => {
+                  val voids = ArrayBuffer[Stmt]()
+                  for (e <- get_female_refs(get_name(s),get_type(s),get_gender(s))) {
+                     voids += Connect(get_info(s),e,WVoid())
+                  }
+                  Begin(Seq(s,Begin(voids)))
+               }
+               case (s) => sMap(void_all_s _,s)
+            }
+         }
+         val voids = ArrayBuffer[Stmt]()
+         for (p <- m.ports) {
+            for (e <- get_female_refs(p.name,p.tpe,get_gender(p))) {
+               voids += Connect(p.info,e,WVoid())
+            }
+         }
+         val bodyx = void_all_s(m.body)
+         voids += bodyx
+         InModule(m.info,m.name,m.ports,Begin(voids))
+      }
+      def expand_whens (m:InModule) : Tuple2[HashMap[WrappedExpression,Expression],ArrayBuffer[Stmt]] = {
+         val simlist = ArrayBuffer[Stmt]()
+         mname = m.name
+         def expand_whens (netlist:HashMap[WrappedExpression,Expression],p:Expression)(s:Stmt) : Stmt = {
+            (s) match {
+               case (s:Connect) => netlist(s.loc) = s.exp
+               case (s:IsInvalid) => netlist(s.exp) = WInvalid()
+               case (s:Conditionally) => {
+                  val exps = ArrayBuffer[Expression]()
+                  def prefetch (s:Stmt) : Stmt = {
+                     (s) match {
+                        case (s:Connect) => exps += s.loc; s
+                        case (s) => sMap(prefetch _,s)
+                     }
+                  }
+                  prefetch(s.conseq)
+                  val c_netlist = get_entries(netlist,exps)
+                  expand_whens(c_netlist,AND(p,s.pred))(s.conseq)
+                  expand_whens(netlist,AND(p,NOT(s.pred)))(s.alt)
+                  for (lvalue <- c_netlist.keys) {
+                     val value = netlist.get(lvalue)
+                     (value) match {
+                        case (value:Some[Expression]) => {
+                           val tv = c_netlist(lvalue)
+                           val fv = value.get
+                           val res = (tv,fv) match {
+                              case (tv:WInvalid,fv:WInvalid) => WInvalid()
+                              case (tv:WInvalid,fv) => ValidIf(NOT(s.pred),fv,tpe(fv))
+                              case (tv,fv:WInvalid) => ValidIf(s.pred,tv,tpe(tv))
+                              case (tv,fv) => Mux(s.pred,tv,fv,mux_type_and_widths(tv,fv))
+                           }
+                           netlist(lvalue) = res
+                        }
+                        case (None) => add(netlist,lvalue,c_netlist(lvalue))
+                     }
+                  }
+               }
+               case (s:Print) => {
+                  if (p == one) {
+                     simlist += s
+                  } else {
+                     simlist += Print(s.info,s.string,s.args,s.clk,AND(p,s.en))
+                  }
+               }
+               case (s:Stop) => {
+                  if (p == one) {
+                     simlist += s
+                  } else {
+                     simlist += Stop(s.info,s.ret,s.clk,AND(p,s.en))
+                  }
+               }
+               case (s) => sMap(expand_whens(netlist,p) _, s)
+            }
+            s
+         }
+         val netlist = HashMap[WrappedExpression,Expression]()
+         expand_whens(netlist,one)(m.body)
+   
+         //println("Netlist:")
+         //println(netlist)
+         //println("Simlist:")
+         //println(simlist)
+         ( netlist, simlist )
+      }
+   
+      def create_module (netlist:HashMap[WrappedExpression,Expression],simlist:ArrayBuffer[Stmt],m:InModule) : InModule = {
+         mname = m.name
+         val stmts = ArrayBuffer[Stmt]()
+         val connections = ArrayBuffer[Stmt]()
+         def replace_void (e:Expression)(rvalue:Expression) : Expression = {
+            (rvalue) match {
+               case (rv:WVoid) => e
+               case (rv) => eMap(replace_void(e) _,rv)
+            }
+         }
+         def create (s:Stmt) : Stmt = {
+            (s) match {
+               case (_:DefWire|_:WDefInstance|_:DefMemory) => {
+                  stmts += s
+                  for (e <- get_female_refs(get_name(s),get_type(s),get_gender(s))) {
+                     val rvalue = netlist(e)
+                     val con = (rvalue) match {
+                        case (rvalue:WInvalid) => IsInvalid(get_info(s),e)
+                        case (rvalue) => Connect(get_info(s),e,rvalue)
+                     }
+                     connections += con
+                  }
+               }
+               case (s:DefRegister) => {
+                  stmts += s
+                  for (e <- get_female_refs(get_name(s),get_type(s),get_gender(s))) {
+                     val rvalue = replace_void(e)(netlist(e))
+                     val con = (rvalue) match {
+                        case (rvalue:WInvalid) => IsInvalid(get_info(s),e)
+                        case (rvalue) => Connect(get_info(s),e,rvalue)
+                     }
+                     connections += con
+                  }
+               }
+               case (_:DefPoison|_:DefNode) => stmts += s
+               case (s) => sMap(create _,s)
+            }
+            s
+         }
+         create(m.body)
+         for (p <- m.ports) {
+            for (e <- get_female_refs(p.name,p.tpe,get_gender(p))) {
+               val rvalue = netlist(e)
+               val con = (rvalue) match {
+                  case (rvalue:WInvalid) => IsInvalid(p.info,e)
+                  case (rvalue) => Connect(p.info,e,rvalue)
+               }
+               connections += con
+            }
+         }
+         for (x <- simlist) { stmts += x }
+         InModule(m.info,m.name,m.ports,Begin(Seq(Begin(stmts),Begin(connections))))
+      }
+   
+      val voided_modules = c.modules.map{ m => {
+            (m) match {
+               case (m:ExModule) => m
+               case (m:InModule) => void_all(m)
+            } } }
+      val modulesx = voided_modules.map{ m => {
+            (m) match {
+               case (m:ExModule) => m
+               case (m:InModule) => {
+                  val (netlist, simlist) = expand_whens(m)
+                  create_module(netlist,simlist,m)
+               }
+            }}}
+      Circuit(c.info,modulesx,c.main)
+   }
 }
 
 object CheckInitialization extends Pass with StanzaPass {