Refactor RemoveAccesses and fix bug #210.

Added corresponding unit test.

1 files changed, 0 insertions, 145 deletions

diff --git a/src/main/scala/firrtl/passes/Passes.scala b/src/main/scala/firrtl/passes/Passes.scala
index 6216d2aa..1a40b7c5 100644
--- a/src/main/scala/firrtl/passes/Passes.scala
+++ b/src/main/scala/firrtl/passes/Passes.scala
@@ -747,151 +747,6 @@ object ExpandConnects extends Pass {
    }
 }
 
-case class Location(base:Expression,guard:Expression)
-object RemoveAccesses extends Pass {
-   private var mname = ""
-   def name = "Remove Accesses"
-   def get_locations (e:Expression) : Seq[Location] = {
-       e match {
-         case (e:WRef) => create_exps(e).map(Location(_,one))
-         case (e:WSubIndex) => {
-            val ls = get_locations(e.exp)
-            val start = get_point(e)
-            val end = start + get_size(tpe(e))
-            val stride = get_size(tpe(e.exp))
-            val lsx = ArrayBuffer[Location]()
-            var c = 0
-            for (i <- 0 until ls.size) {
-               if (((i % stride) >= start) & ((i % stride) < end)) {
-                  lsx += ls(i)
-               }
-            }
-            lsx
-         }
-         case (e:WSubField) => {
-            val ls = get_locations(e.exp)
-            val start = get_point(e)
-            val end = start + get_size(tpe(e))
-            val stride = get_size(tpe(e.exp))
-            val lsx = ArrayBuffer[Location]()
-            var c = 0
-            for (i <- 0 until ls.size) {
-               if (((i % stride) >= start) & ((i % stride) < end)) { lsx += ls(i) }
-            }
-            lsx
-         }
-         case (e:WSubAccess) => {
-            val ls = get_locations(e.exp)
-            val stride = get_size(tpe(e))
-            val wrap = tpe(e.exp).asInstanceOf[VectorType].size
-            val lsx = ArrayBuffer[Location]()
-            var c = 0
-            for (i <- 0 until ls.size) {
-               if ((c % wrap) == 0) { c = 0 }
-               val basex = ls(i).base
-               val guardx = AND(ls(i).guard,EQV(uint(c),e.index))
-               lsx += Location(basex,guardx)
-               if ((i + 1) % stride == 0) {
-                  c = c + 1
-               }
-            }
-            lsx
-         }
-      }
-   }
-   def has_access (e:Expression) : Boolean = {
-      var ret:Boolean = false
-      def rec_has_access (e:Expression) : Expression = {
-         e match {
-            case (e:WSubAccess) => { ret = true; e }
-            case (e) => e map (rec_has_access)
-         }
-      }
-      rec_has_access(e)
-      ret
-   }
-   def run (c:Circuit): Circuit = {
-      def remove_m (m:Module) : Module = {
-         val namespace = Namespace(m)
-         mname = m.name
-         def remove_s (s:Statement) : Statement = {
-            val stmts = ArrayBuffer[Statement]()
-            def create_temp (e:Expression) : Expression = {
-               val n = namespace.newTemp
-               stmts += DefWire(info(s),n,tpe(e))
-               WRef(n,tpe(e),kind(e),gender(e))
-            }
-            def remove_e (e:Expression) : Expression = { //NOT RECURSIVE (except primops) INTENTIONALLY!
-               e match {
-                  case (e:DoPrim) => e map (remove_e)
-                  case (e:Mux) => e map (remove_e)
-                  case (e:ValidIf) => e map (remove_e)
-                  case (e:SIntLiteral) => e
-                  case (e:UIntLiteral) => e
-                  case x => {
-                     val e = x match {
-                        case (w:WSubAccess) => WSubAccess(w.exp,remove_e(w.index),w.tpe,w.gender)
-                        case _ => x
-                     }
-                     if (has_access(e)) {
-                        val rs = get_locations(e)
-                        val foo = rs.find(x => {x.guard != one})
-                        foo match {
-                           case None => error("Shouldn't be here")
-                           case foo:Some[Location] => {
-                              val temp = create_temp(e)
-                              val temps = create_exps(temp)
-                              def get_temp (i:Int) = temps(i % temps.size)
-                              (rs,0 until rs.size).zipped.foreach {
-                                 (x,i) => {
-                                    if (i < temps.size) {
-                                       stmts += Connect(info(s),get_temp(i),x.base)
-                                    } else {
-                                       stmts += Conditionally(info(s),x.guard,Connect(info(s),get_temp(i),x.base),EmptyStmt)
-                                    }
-                                 }
-                              }
-                              temp
-                           }
-                        }
-                     } else { e}
-                  }
-               }
-            }
-
-            val sx = s match {
-               case (s:Connect) => {
-                  if (has_access(s.loc)) {
-                     val ls = get_locations(s.loc)
-                     val locx = 
-                        if (ls.size == 1 & weq(ls(0).guard,one)) s.loc
-                        else {
-                           val temp = create_temp(s.loc)
-                           for (x <- ls) { stmts += Conditionally(s.info,x.guard,Connect(s.info,x.base,temp),EmptyStmt) }
-                           temp
-                        }
-                     Connect(s.info,locx,remove_e(s.expr))
-                  } else { Connect(s.info,s.loc,remove_e(s.expr)) }
-               }
-               case (s) => s map (remove_e) map (remove_s)
-            }
-            stmts += sx
-            if (stmts.size != 1) Block(stmts) else stmts(0)
-         }
-         Module(m.info,m.name,m.ports,remove_s(m.body))
-      }
-   
-      val modulesx = c.modules.map{
-         m => {
-            m match {
-               case (m:ExtModule) => m
-               case (m:Module) => remove_m(m)
-            }
-         }
-      }
-      Circuit(c.info,modulesx,c.main)
-   }
-}
 
 // Replace shr by amount >= arg width with 0 for UInts and MSB for SInts
 // TODO replace UInt with zero-width wire instead