aboutsummaryrefslogtreecommitdiff
path: root/src/main/scala/firrtl/passes/MemUtils.scala
diff options
context:
space:
mode:
authorJack Koenig2016-09-13 13:15:04 -0700
committerGitHub2016-09-13 13:15:04 -0700
commitad36a1216f52bc01a27dac93cfd8cd42beb84c73 (patch)
tree1c65e06819baf90e1e86fa65ebe68e327de38461 /src/main/scala/firrtl/passes/MemUtils.scala
parent066dc5010a9ebaed276b064451e259318052865e (diff)
parent9a68008856f390bdc3be858f9cce5ed484cdb68f (diff)
Merge pull request #296 from ucb-bar/fix-bits-type-take3
Fix bits type
Diffstat (limited to 'src/main/scala/firrtl/passes/MemUtils.scala')
-rw-r--r--src/main/scala/firrtl/passes/MemUtils.scala3
1 files changed, 1 insertions, 2 deletions
diff --git a/src/main/scala/firrtl/passes/MemUtils.scala b/src/main/scala/firrtl/passes/MemUtils.scala
index b235213a..adbf23e5 100644
--- a/src/main/scala/firrtl/passes/MemUtils.scala
+++ b/src/main/scala/firrtl/passes/MemUtils.scala
@@ -83,8 +83,7 @@ object bitWidth {
def widthOf(dt: Type): BigInt = dt match {
case t: VectorType => t.size * bitWidth(t.tpe)
case t: BundleType => t.fields.map(f => bitWidth(f.tpe)).foldLeft(BigInt(0))(_+_)
- case UIntType(IntWidth(width)) => width
- case SIntType(IntWidth(width)) => width
+ case GroundType(IntWidth(width)) => width
case t => error("Unknown type encountered in bitWidth!")
}
}