diff options
| author | Andrew Waterman | 2016-09-13 20:54:20 -0700 |
|---|---|---|
| committer | Donggyu | 2016-09-13 20:54:20 -0700 |
| commit | 8fc37582267b2319e5fa25818fcd1346d8e180ae (patch) | |
| tree | 2a9e2ae060cb7be6b417408d3cbd3e282cc690bc /src/main/scala/firrtl/passes/MemUtils.scala | |
| parent | 36c19ed40bec120ef38aefa7e2c875c5e21bf048 (diff) | |
Fix a lurking width-inference bug; improve adjacent style (#298)
ceil(log(x) / log(2)) does not, in general, round to ceil(log2(x)).
I noticed this because of #297.
Diffstat (limited to 'src/main/scala/firrtl/passes/MemUtils.scala')
| -rw-r--r-- | src/main/scala/firrtl/passes/MemUtils.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/scala/firrtl/passes/MemUtils.scala b/src/main/scala/firrtl/passes/MemUtils.scala index 505ad0da..d2557f8d 100644 --- a/src/main/scala/firrtl/passes/MemUtils.scala +++ b/src/main/scala/firrtl/passes/MemUtils.scala @@ -152,7 +152,7 @@ object MemPortUtils { def flattenType(t: Type) = UIntType(IntWidth(bitWidth(t))) def defaultPortSeq(mem: DefMemory) = Seq( - Field("addr", Default, UIntType(IntWidth(ceil_log2(mem.depth) max 1))), + Field("addr", Default, UIntType(IntWidth(ceilLog2(mem.depth) max 1))), Field("en", Default, BoolType), Field("clk", Default, ClockType) ) |