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authorDonggyu Kim2016-09-02 17:28:39 -0700
committerDonggyu Kim2016-09-13 13:36:38 -0700
commit4cb46ca17da26c7ccc0b66a6be489a49fb2e9173 (patch)
treea283ed9716f10cee128a9a782dada088bba97d5f /src/main/scala/firrtl/passes/MemUtils.scala
parent590c3f2cd959c3c125c6511287294aec8409b57b (diff)
remove Utils.{width_BANG, long_BANG}
Diffstat (limited to 'src/main/scala/firrtl/passes/MemUtils.scala')
-rw-r--r--src/main/scala/firrtl/passes/MemUtils.scala8
1 files changed, 8 insertions, 0 deletions
diff --git a/src/main/scala/firrtl/passes/MemUtils.scala b/src/main/scala/firrtl/passes/MemUtils.scala
index 798b02da..87033176 100644
--- a/src/main/scala/firrtl/passes/MemUtils.scala
+++ b/src/main/scala/firrtl/passes/MemUtils.scala
@@ -82,6 +82,14 @@ object toBitMask {
}
}
+object getWidth {
+ def apply(t: Type): Width = t match {
+ case t: GroundType => t.width
+ case _ => error("No width!")
+ }
+ def apply(e: Expression): Width = apply(e.tpe)
+}
+
object bitWidth {
def apply(dt: Type): BigInt = widthOf(dt)
private def widthOf(dt: Type): BigInt = dt match {