diff options
| author | Donggyu | 2016-09-13 19:51:31 -0700 |
|---|---|---|
| committer | GitHub | 2016-09-13 19:51:31 -0700 |
| commit | 36c19ed40bec120ef38aefa7e2c875c5e21bf048 (patch) | |
| tree | 15b3983afce32430c2a333459286e77dc106cd56 /src/main/scala/firrtl/passes/MemUtils.scala | |
| parent | d832d6d1e36be43c958c81b1ca347f2c413eed49 (diff) | |
| parent | 41c78f9854124986e812fd7c7363d404fdb64b0b (diff) | |
Merge pull request #291 from ucb-bar/case_object_WVoid_WInvalid
Case object for WVoid WInvalid
Diffstat (limited to 'src/main/scala/firrtl/passes/MemUtils.scala')
| -rw-r--r-- | src/main/scala/firrtl/passes/MemUtils.scala | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/main/scala/firrtl/passes/MemUtils.scala b/src/main/scala/firrtl/passes/MemUtils.scala index 21884661..505ad0da 100644 --- a/src/main/scala/firrtl/passes/MemUtils.scala +++ b/src/main/scala/firrtl/passes/MemUtils.scala @@ -193,7 +193,7 @@ object MemPortUtils { def rwPortToFlattenBundle(mem: DefMemory) = BundleType( defaultPortSeq(mem) ++ Seq( - Field("wmode", Default, UIntType(IntWidth(1))), + Field("wmode", Default, BoolType), Field("wdata", Default, flattenType(mem.dataType)), Field("rdata", Flip, flattenType(mem.dataType)) ) ++ (if (!containsInfo(mem.info, "maskGran")) Nil @@ -220,7 +220,7 @@ object MemPortUtils { Field("mask", Default, createMask(mem.dataType)))) val rwType = BundleType(defaultPortSeq(mem) ++ Seq( Field("rdata", Flip, mem.dataType), - Field("wmode", Default, UIntType(IntWidth(1))), + Field("wmode", Default, BoolType), Field("wdata", Default, mem.dataType), Field("wmask", Default, createMask(mem.dataType)))) BundleType( |