diff options
| author | Angie Wang | 2016-08-17 13:34:14 -0700 |
|---|---|---|
| committer | Jack Koenig | 2016-08-17 13:34:14 -0700 |
| commit | 5db4abebb7ceb5939a9efca158d78e3dc0e32c44 (patch) | |
| tree | fd8c5b5231a8f097962a5c7c95a079b79e8e9d4f /src/main/scala/firrtl/passes/InferReadWrite.scala | |
| parent | 673d7c6e11c80d7439a416b4dcb206e6777d89cf (diff) | |
Change RW port names (#236)
* Updated FIRRTL spec + related code for readwrite ports.
(write) data -> wdata & mask -> wmask for clarity
* Also removed simple.fir that snuck into master branch.
Diffstat (limited to 'src/main/scala/firrtl/passes/InferReadWrite.scala')
| -rw-r--r-- | src/main/scala/firrtl/passes/InferReadWrite.scala | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/main/scala/firrtl/passes/InferReadWrite.scala b/src/main/scala/firrtl/passes/InferReadWrite.scala index 2378216d..664b3dfc 100644 --- a/src/main/scala/firrtl/passes/InferReadWrite.scala +++ b/src/main/scala/firrtl/passes/InferReadWrite.scala @@ -139,8 +139,8 @@ object InferReadWritePass extends Pass { repl(s"${mem.name}.$w.en") = WSubField(rw_exp, "wmode", bt, FEMALE) repl(s"${mem.name}.$w.clk") = EmptyExpression repl(s"${mem.name}.$w.addr") = EmptyExpression - repl(s"${mem.name}.$w.data") = WSubField(rw_exp, "data", mem.dataType, FEMALE) - repl(s"${mem.name}.$w.mask") = WSubField(rw_exp, "mask", ut, FEMALE) + repl(s"${mem.name}.$w.data") = WSubField(rw_exp, "wdata", mem.dataType, FEMALE) + repl(s"${mem.name}.$w.mask") = WSubField(rw_exp, "wmask", ut, FEMALE) stmts += Connect(NoInfo, WSubField(rw_exp, "clk", ClockType, FEMALE), WRef("clk", ClockType, NodeKind(), MALE)) stmts += Connect(NoInfo, WSubField(rw_exp, "en", bt, FEMALE), |