diff options
| author | Chick Markley | 2016-10-11 15:53:40 -0700 |
|---|---|---|
| committer | Adam Izraelevitz | 2016-10-11 15:53:40 -0700 |
| commit | 2848d87721df110d0425114283cb5fa7e6c2ee03 (patch) | |
| tree | d76dd381fb77d63b8509a69063ace380f3209f33 /src/main/scala/firrtl/passes/InferReadWrite.scala | |
| parent | 515f29f5993abb399db43b04e9a63c0fdf347ecc (diff) | |
Scala style cleanup take 5 (#324)
* working through variable shrouding
* working through variable shrouding
* working through variable shadowing
* working through variable shadowing
hmm there are some very fragile match {} in Passes
* working through variable shadowing
hmm there are some very fragile match {} in Passes
* working through variable shadowing
* working through variable shadowing
* working through variable shadowing
* working through variable shadowing
* working through variable shadowing
* working through variable shadowing
* working through variable shadowing
* working through variable shadowing
* Fixes suggested by Adam
Diffstat (limited to 'src/main/scala/firrtl/passes/InferReadWrite.scala')
| -rw-r--r-- | src/main/scala/firrtl/passes/InferReadWrite.scala | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/main/scala/firrtl/passes/InferReadWrite.scala b/src/main/scala/firrtl/passes/InferReadWrite.scala index f863c7e7..a1875ae7 100644 --- a/src/main/scala/firrtl/passes/InferReadWrite.scala +++ b/src/main/scala/firrtl/passes/InferReadWrite.scala @@ -92,14 +92,14 @@ object InferReadWritePass extends Pass { def replaceExp(repl: Netlist)(e: Expression): Expression = e map replaceExp(repl) match { - case e: WSubField => repl getOrElse (e.serialize, e) - case e => e + case ex: WSubField => repl getOrElse (ex.serialize, ex) + case ex => ex } def replaceStmt(repl: Netlist)(s: Statement): Statement = s map replaceStmt(repl) map replaceExp(repl) match { case Connect(_, EmptyExpression, _) => EmptyStmt - case s => s + case sx => sx } def inferReadWriteStmt(connects: Connects, @@ -148,7 +148,7 @@ object InferReadWritePass extends Pass { readers = mem.readers filterNot readers, writers = mem.writers filterNot writers, readwriters = mem.readwriters ++ readwriters) - case s => s map inferReadWriteStmt(connects, repl, stmts) + case sx => sx map inferReadWriteStmt(connects, repl, stmts) } def inferReadWrite(m: DefModule) = { |