Added a Chirrtl check for undeclared wires, etc.

1 files changed, 0 insertions, 18 deletions

diff --git a/src/main/scala/firrtl/passes/Checks.scala b/src/main/scala/firrtl/passes/Checks.scala
index 94d509ed..a6762372 100644
--- a/src/main/scala/firrtl/passes/Checks.scala
+++ b/src/main/scala/firrtl/passes/Checks.scala
@@ -63,24 +63,6 @@ object CheckHighForm extends Pass with LazyLogging {
   class BadPrintfTrailingException extends PassException(s"${sinfo}: [module ${mname}] Bad printf format: trailing " + "\"%\"")
   class BadPrintfIncorrectNumException extends PassException(s"${sinfo}: [module ${mname}] Bad printf format: incorrect number of arguments")
 
-  // Utility functions
-  def hasFlip(t: Type): Boolean = {
-    var has = false
-    def findFlip(t: Type): Type = {
-      t map (findFlip) match {
-        case t: BundleType => {
-          for (f <- t.fields) {
-            if (f.flip == Flip) has = true
-          }
-          t
-        }
-        case t: Type => t
-      }
-    }
-    findFlip(t)
-    has
-  }
-
   // TODO FIXME
   // - Do we need to check for uniquness on port names?
   // Global Variables