diff options
| author | chick | 2020-08-14 19:47:53 -0700 |
|---|---|---|
| committer | Jack Koenig | 2020-08-14 19:47:53 -0700 |
| commit | 6fc742bfaf5ee508a34189400a1a7dbffe3f1cac (patch) | |
| tree | 2ed103ee80b0fba613c88a66af854ae9952610ce /src/main/scala/firrtl/analyses/InstanceGraph.scala | |
| parent | b516293f703c4de86397862fee1897aded2ae140 (diff) | |
All of src/ formatted with scalafmt
Diffstat (limited to 'src/main/scala/firrtl/analyses/InstanceGraph.scala')
| -rw-r--r-- | src/main/scala/firrtl/analyses/InstanceGraph.scala | 30 |
1 files changed, 13 insertions, 17 deletions
diff --git a/src/main/scala/firrtl/analyses/InstanceGraph.scala b/src/main/scala/firrtl/analyses/InstanceGraph.scala index f994b39a..4aab9a3a 100644 --- a/src/main/scala/firrtl/analyses/InstanceGraph.scala +++ b/src/main/scala/firrtl/analyses/InstanceGraph.scala @@ -10,7 +10,6 @@ import firrtl.Utils._ import firrtl.traversals.Foreachers._ import firrtl.annotations.TargetToken._ - /** A class representing the instance hierarchy of a working IR Circuit * * @constructor constructs an instance graph from a Circuit @@ -29,7 +28,7 @@ import firrtl.annotations.TargetToken._ class InstanceGraph(c: Circuit) { @deprecated("Use InstanceKeyGraph.moduleMap instead.", "FIRRTL 1.4") - val moduleMap = c.modules.map({m => (m.name,m) }).toMap + val moduleMap = c.modules.map({ m => (m.name, m) }).toMap private val instantiated = new mutable.LinkedHashSet[String] private val childInstances = new mutable.LinkedHashMap[String, mutable.LinkedHashSet[DefInstance]] @@ -43,7 +42,7 @@ class InstanceGraph(c: Circuit) { private val instanceQueue = new mutable.Queue[DefInstance] for (subTop <- c.modules.view.map(_.name).filterNot(instantiated)) { - val topInstance = DefInstance(subTop,subTop) + val topInstance = DefInstance(subTop, subTop) instanceQueue.enqueue(topInstance) while (instanceQueue.nonEmpty) { val current = instanceQueue.dequeue @@ -53,7 +52,7 @@ class InstanceGraph(c: Circuit) { instanceQueue.enqueue(child) instanceGraph.addVertex(child) } - instanceGraph.addEdge(current,child) + instanceGraph.addEdge(current, child) } } } @@ -73,7 +72,7 @@ class InstanceGraph(c: Circuit) { * of all module instances in the Circuit. */ @deprecated("Use InstanceKeyGraph.fullHierarchy instead.", "FIRRTL 1.4") - lazy val fullHierarchy: mutable.LinkedHashMap[DefInstance,Seq[Seq[DefInstance]]] = graph.pathsInDAG(trueTopInstance) + lazy val fullHierarchy: mutable.LinkedHashMap[DefInstance, Seq[Seq[DefInstance]]] = graph.pathsInDAG(trueTopInstance) /** A count of the *static* number of instances of each module. For any module other than the top (main) module, this is * equivalent to the number of inst statements in the circuit instantiating each module, irrespective of the number @@ -85,7 +84,7 @@ class InstanceGraph(c: Circuit) { lazy val staticInstanceCount: Map[OfModule, Int] = { val foo = mutable.LinkedHashMap.empty[OfModule, Int] childInstances.keys.foreach { - case main if main == c.main => foo += main.OfModule -> 1 + case main if main == c.main => foo += main.OfModule -> 1 case other => foo += other.OfModule -> 0 } childInstances.values.flatten.map(_.OfModule).foreach { @@ -106,7 +105,7 @@ class InstanceGraph(c: Circuit) { @deprecated("Use InstanceKeyGraph.findInstancesInHierarchy instead (now with caching of vertices!).", "FIRRTL 1.4") def findInstancesInHierarchy(module: String): Seq[Seq[DefInstance]] = { val instances = graph.getVertices.filter(_.module == module).toSeq - instances flatMap { i => fullHierarchy.getOrElse(i, Nil) } + instances.flatMap { i => fullHierarchy.getOrElse(i, Nil) } } /** An [[firrtl.graph.EulerTour EulerTour]] representation of the [[firrtl.graph.DiGraph DiGraph]] */ @@ -117,8 +116,7 @@ class InstanceGraph(c: Circuit) { * a design */ @deprecated("Use InstanceKeyGraph and EulerTour(iGraph.graph, iGraph.top).rmq(moduleA, moduleB).", "FIRRTL 1.4") - def lowestCommonAncestor(moduleA: Seq[DefInstance], - moduleB: Seq[DefInstance]): Seq[DefInstance] = { + def lowestCommonAncestor(moduleA: Seq[DefInstance], moduleB: Seq[DefInstance]): Seq[DefInstance] = { tour.rmq(moduleA, moduleB) } @@ -131,10 +129,9 @@ class InstanceGraph(c: Circuit) { graph.transformNodes(_.module).linearize.map(moduleMap(_)) } - /** Given a circuit, returns a map from module name to children - * instance/module definitions - */ + * instance/module definitions + */ @deprecated("Use InstanceKeyGraph.getChildInstances instead.", "FIRRTL 1.4") def getChildrenInstances: mutable.LinkedHashMap[String, mutable.LinkedHashSet[DefInstance]] = childInstances @@ -172,7 +169,7 @@ class InstanceGraph(c: Circuit) { /** The set of all modules *not* reachable in the circuit */ @deprecated("Use InstanceKeyGraph.unreachableModules instead.", "FIRRTL 1.4") - lazy val unreachableModules: collection.Set[OfModule] = modules diff reachableModules + lazy val unreachableModules: collection.Set[OfModule] = modules.diff(reachableModules) } @@ -186,10 +183,9 @@ object InstanceGraph { * @return */ @deprecated("Use InstanceKeyGraph.collectInstances instead.", "FIRRTL 1.4") - def collectInstances(insts: mutable.Set[DefInstance]) - (s: Statement): Unit = s match { - case i: DefInstance => insts += i - case i: DefInstance => throwInternalError("Expecting DefInstance, found a DefInstance!") + def collectInstances(insts: mutable.Set[DefInstance])(s: Statement): Unit = s match { + case i: DefInstance => insts += i + case i: DefInstance => throwInternalError("Expecting DefInstance, found a DefInstance!") case i: WDefInstanceConnector => throwInternalError("Expecting DefInstance, found a DefInstanceConnector!") case _ => s.foreach(collectInstances(insts)) } |
