Everything is broken, need Translator to work on files without a circuit, need to parse queue module text in midas/Utils.scala, need to create (src, dst) -> Module mapping in midas/Fame.scala

1 files changed, 23 insertions, 0 deletions

diff --git a/src/main/scala/firrtl/Parser.scala b/src/main/scala/firrtl/Parser.scala
index 35e41222..40956ab7 100644
--- a/src/main/scala/firrtl/Parser.scala
+++ b/src/main/scala/firrtl/Parser.scala
@@ -11,6 +11,29 @@ import antlr._
 
 object Parser
 {
+  def parseModule(string: String): Module = {
+    val fixedInput = Translator.addBrackets(Iterator(string))
+    val antlrStream = new ANTLRInputStream(fixedInput.result)
+    val lexer = new FIRRTLLexer(antlrStream)
+    val tokens = new CommonTokenStream(lexer)
+    val parser = new FIRRTLParser(tokens)
+
+    // FIXME Dangerous
+    parser.getInterpreter.setPredictionMode(PredictionMode.SLL)
+
+    // Concrete Syntax Tree
+    val cst = parser.module
+
+    val visitor = new Visitor("none") 
+    //val ast = visitor.visitCircuit(cst) match {
+    val ast = visitor.visit(cst) match {
+      case m: Module => m
+      case x => throw new ClassCastException("Error! AST not rooted with Module node!")
+    }
+
+    ast
+
+  }
 
   /** Takes a firrtl filename, returns AST (root node is Circuit)
     *