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authorJack Koenig2017-06-22 14:52:24 -0700
committerJack Koenig2017-06-27 18:50:15 -0700
commitca01018fb144dcd206735973e5aa302dbc552ea8 (patch)
treec282e0dfe37de7a49271d9a1da364606fe35cf1a /src/main/scala/firrtl/LoweringCompilers.scala
parent6f55a30b201716b6a0e72b65f6e5777b6b5d4b81 (diff)
Add RemoveReset transform to replace register reset with a Mux
Diffstat (limited to 'src/main/scala/firrtl/LoweringCompilers.scala')
-rw-r--r--src/main/scala/firrtl/LoweringCompilers.scala1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/main/scala/firrtl/LoweringCompilers.scala b/src/main/scala/firrtl/LoweringCompilers.scala
index 0df052af..66ae1673 100644
--- a/src/main/scala/firrtl/LoweringCompilers.scala
+++ b/src/main/scala/firrtl/LoweringCompilers.scala
@@ -85,6 +85,7 @@ class MiddleFirrtlToLowFirrtl extends CoreTransform {
passes.ResolveGenders,
passes.InferWidths,
passes.Legalize,
+ new firrtl.transforms.RemoveReset,
new firrtl.transforms.CheckCombLoops)
}