Reworked annotation system. Added tenacity and permissibility

Conflicts:
	src/main/scala/firrtl/Compiler.scala
	src/main/scala/firrtl/LoweringCompilers.scala
	src/main/scala/firrtl/passes/Inline.scala
	src/test/scala/firrtlTests/AnnotationTests.scala
	src/test/scala/firrtlTests/InlineInstancesTests.scala

1 files changed, 11 insertions, 9 deletions

diff --git a/src/main/scala/firrtl/LoweringCompilers.scala b/src/main/scala/firrtl/LoweringCompilers.scala
index 036156dc..8beaf7f9 100644
--- a/src/main/scala/firrtl/LoweringCompilers.scala
+++ b/src/main/scala/firrtl/LoweringCompilers.scala
@@ -31,6 +31,7 @@ import com.typesafe.scalalogging.LazyLogging
 import java.io.Writer
 import firrtl.passes.Pass
 import firrtl.ir.Circuit
+import Annotations._
 
 // ===========================================
 //              Utility Traits
@@ -65,7 +66,7 @@ class Chisel3ToHighFirrtl () extends Transform with SimpleRun {
       passes.CInferTypes,
       passes.CInferMDir,
       passes.RemoveCHIRRTL)
-   def execute (circuit: Circuit, annotations: Seq[CircuitAnnotation]): TransformResult =
+   def execute (circuit: Circuit, annotationMap: AnnotationMap): TransformResult =
       run(circuit, passSeq)
 }
 
@@ -73,7 +74,7 @@ class Chisel3ToHighFirrtl () extends Transform with SimpleRun {
 //  to a working representation (WIR.scala)
 class IRToWorkingIR () extends Transform with SimpleRun {
    val passSeq = Seq(passes.ToWorkingIR)
-   def execute (circuit: Circuit, annotations: Seq[CircuitAnnotation]): TransformResult =
+   def execute (circuit: Circuit, annotationMap: AnnotationMap): TransformResult =
       run(circuit, passSeq)
 }
 
@@ -92,7 +93,7 @@ class ResolveAndCheck () extends Transform with SimpleRun {
       passes.CheckGenders,
       passes.InferWidths,
       passes.CheckWidths)
-   def execute (circuit: Circuit, annotations: Seq[CircuitAnnotation]): TransformResult =
+   def execute (circuit: Circuit, annotationMap: AnnotationMap): TransformResult =
       run(circuit, passSeq)
 }
 
@@ -107,12 +108,13 @@ class HighFirrtlToMiddleFirrtl () extends Transform with SimpleRun {
       passes.RemoveAccesses,
       passes.ExpandWhens,
       passes.CheckInitialization,
+      passes.ConstProp,
       passes.ResolveKinds,
       passes.InferTypes,
       passes.ResolveGenders)
       //passes.InferWidths,
       //passes.CheckWidths)
-   def execute (circuit: Circuit, annotations: Seq[CircuitAnnotation]): TransformResult =
+   def execute (circuit: Circuit, annotationMap: AnnotationMap): TransformResult =
       run(circuit, passSeq)
 }
 
@@ -128,7 +130,7 @@ class MiddleFirrtlToLowFirrtl () extends Transform with SimpleRun {
       passes.InferTypes,
       passes.ResolveGenders,
       passes.InferWidths)
-   def execute (circuit: Circuit, annotations: Seq[CircuitAnnotation]): TransformResult =
+   def execute (circuit: Circuit, annotationMap: AnnotationMap): TransformResult =
       run(circuit, passSeq)
 }
 
@@ -149,7 +151,7 @@ class EmitVerilogFromLowFirrtl (val writer: Writer) extends Transform with Simpl
       passes.CommonSubexpressionElimination,
       passes.DeadCodeElimination,
       passes.VerilogRename)
-   def execute (circuit: Circuit, annotations: Seq[CircuitAnnotation]): TransformResult = {
+   def execute (circuit: Circuit, annotationMap: AnnotationMap): TransformResult = {
       val result = run(circuit, passSeq)
       (new VerilogEmitter).run(result.circuit, writer)
       result
@@ -159,7 +161,7 @@ class EmitVerilogFromLowFirrtl (val writer: Writer) extends Transform with Simpl
 // Emits Firrtl.
 // Operates on WIR/IR nodes.
 class EmitFirrtl (val writer: Writer) extends Transform {
-   def execute (circuit: Circuit, annotations: Seq[CircuitAnnotation]): TransformResult = {
+   def execute (circuit: Circuit, annotationMap: AnnotationMap): TransformResult = {
       FIRRTLEmitter.run(circuit, writer)
       TransformResult(circuit)
    }
@@ -184,7 +186,7 @@ class LowFirrtlCompiler extends Compiler {
    def transforms(writer: Writer): Seq[Transform] = Seq(
       new Chisel3ToHighFirrtl(),
       new IRToWorkingIR(),
-      passes.InlineInstances,
+      new passes.InlineInstances(TransID(0)),
       new ResolveAndCheck(),
       new HighFirrtlToMiddleFirrtl(),
       new MiddleFirrtlToLowFirrtl(),
@@ -200,7 +202,7 @@ class VerilogCompiler extends Compiler {
       new ResolveAndCheck(),
       new HighFirrtlToMiddleFirrtl(),
       new MiddleFirrtlToLowFirrtl(),
-      passes.InlineInstances,
+      new passes.InlineInstances(TransID(0)),
       new EmitVerilogFromLowFirrtl(writer)
    )
 }