diff options
| author | Donggyu Kim | 2016-08-31 20:43:06 -0700 |
|---|---|---|
| committer | Donggyu Kim | 2016-09-25 15:02:40 -0700 |
| commit | 350b0d5249c33880f867f41d4e8a0d6ffb87423f (patch) | |
| tree | d08bd63808f505e09a35d68c7997722e62b64fea /src/main/scala/firrtl/LoweringCompilers.scala | |
| parent | 82f89488cacf5826607b0e17b0d29af7c7627c27 (diff) | |
offload latency pipe generation for memories from VerilogEmitter
discussed with @azidar
Diffstat (limited to 'src/main/scala/firrtl/LoweringCompilers.scala')
| -rw-r--r-- | src/main/scala/firrtl/LoweringCompilers.scala | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/main/scala/firrtl/LoweringCompilers.scala b/src/main/scala/firrtl/LoweringCompilers.scala index cd77fa3e..c7b7f5dd 100644 --- a/src/main/scala/firrtl/LoweringCompilers.scala +++ b/src/main/scala/firrtl/LoweringCompilers.scala @@ -145,6 +145,8 @@ class EmitVerilogFromLowFirrtl(val writer: Writer) extends Transform with Simple passes.ConstProp, passes.Legalize, passes.VerilogWrap, + passes.VerilogMemDelays, + passes.ConstProp, passes.SplitExpressions, passes.CommonSubexpressionElimination, passes.DeadCodeElimination, |