diff options
| author | Angie | 2016-08-19 17:00:11 -0700 |
|---|---|---|
| committer | jackkoenig | 2016-09-06 00:17:17 -0700 |
| commit | 0d5fa689a45693bf6db9bc6d9dc3f150bc3ff4b8 (patch) | |
| tree | fa2f12be17f3d1c2075a3af67e40a2b8aeaa2f55 /src/main/scala/firrtl/LoweringCompilers.scala | |
| parent | c1ca57452af8adc00bef92e2ddf8984c8cde5620 (diff) | |
Added starter code for SMem replacement
Diffstat (limited to 'src/main/scala/firrtl/LoweringCompilers.scala')
| -rw-r--r-- | src/main/scala/firrtl/LoweringCompilers.scala | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/main/scala/firrtl/LoweringCompilers.scala b/src/main/scala/firrtl/LoweringCompilers.scala index 7c239b10..f9a5864c 100644 --- a/src/main/scala/firrtl/LoweringCompilers.scala +++ b/src/main/scala/firrtl/LoweringCompilers.scala @@ -189,6 +189,7 @@ class LowFirrtlCompiler extends Compiler { new ResolveAndCheck(), new HighFirrtlToMiddleFirrtl(), new passes.InferReadWrite(TransID(-1)), + new passes.ReplSeqMem(TransID(-2)), new MiddleFirrtlToLowFirrtl(), new EmitFirrtl(writer) ) @@ -202,6 +203,7 @@ class VerilogCompiler extends Compiler { new ResolveAndCheck(), new HighFirrtlToMiddleFirrtl(), new passes.InferReadWrite(TransID(-1)), + new passes.ReplSeqMem(TransID(-2)), new MiddleFirrtlToLowFirrtl(), new passes.InlineInstances(TransID(0)), new EmitVerilogFromLowFirrtl(writer) |