diff options
| author | Jack Koenig | 2017-12-12 16:06:31 -0800 |
|---|---|---|
| committer | GitHub | 2017-12-12 16:06:31 -0800 |
| commit | df579547f769843b76922dbb055ea26839b1d7d4 (patch) | |
| tree | f557811fb961a3125bbfef95815eb81f72ca8346 /src/main/scala/firrtl/LoweringCompilers.scala | |
| parent | 0fd0c66adcf1226ee5947cdaa5629bf59c4123f1 (diff) | |
| parent | 0d794d57df7b388109d7a0834d3b5be8f79892be (diff) | |
Merge pull request #684 from freechipsproject/remove-wires
Remove wires, replacing them with nodes
Diffstat (limited to 'src/main/scala/firrtl/LoweringCompilers.scala')
| -rw-r--r-- | src/main/scala/firrtl/LoweringCompilers.scala | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/main/scala/firrtl/LoweringCompilers.scala b/src/main/scala/firrtl/LoweringCompilers.scala index 8dd9b180..f032868a 100644 --- a/src/main/scala/firrtl/LoweringCompilers.scala +++ b/src/main/scala/firrtl/LoweringCompilers.scala @@ -86,7 +86,8 @@ class MiddleFirrtlToLowFirrtl extends CoreTransform { passes.InferWidths, passes.Legalize, new firrtl.transforms.RemoveReset, - new firrtl.transforms.CheckCombLoops) + new firrtl.transforms.CheckCombLoops, + new firrtl.transforms.RemoveWires) } /** Runs a series of optimization passes on LowFirrtl |