From e39609a2bfbbd108fa1e5044e9c270685d75a816 Mon Sep 17 00:00:00 2001
From: Jack Koenig
Date: Thu, 9 Nov 2017 19:02:43 -0800
Subject: Add RemoveWires transform

This transform replaces all wires with nodes in a legal, flow-forward
order
---
 src/main/scala/firrtl/LoweringCompilers.scala | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

(limited to 'src/main/scala/firrtl/LoweringCompilers.scala')

diff --git a/src/main/scala/firrtl/LoweringCompilers.scala b/src/main/scala/firrtl/LoweringCompilers.scala
index 8dd9b180..f032868a 100644
--- a/src/main/scala/firrtl/LoweringCompilers.scala
+++ b/src/main/scala/firrtl/LoweringCompilers.scala
@@ -86,7 +86,8 @@ class MiddleFirrtlToLowFirrtl extends CoreTransform {
     passes.InferWidths,
     passes.Legalize,
     new firrtl.transforms.RemoveReset,
-    new firrtl.transforms.CheckCombLoops)
+    new firrtl.transforms.CheckCombLoops,
+    new firrtl.transforms.RemoveWires)
 }
 
 /** Runs a series of optimization passes on LowFirrtl
-- 
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