diff options
| author | Jack Koenig | 2016-09-13 13:15:04 -0700 |
|---|---|---|
| committer | GitHub | 2016-09-13 13:15:04 -0700 |
| commit | ad36a1216f52bc01a27dac93cfd8cd42beb84c73 (patch) | |
| tree | 1c65e06819baf90e1e86fa65ebe68e327de38461 /src/main/scala/firrtl/LoweringCompilers.scala | |
| parent | 066dc5010a9ebaed276b064451e259318052865e (diff) | |
| parent | 9a68008856f390bdc3be858f9cce5ed484cdb68f (diff) | |
Merge pull request #296 from ucb-bar/fix-bits-type-take3
Fix bits type
Diffstat (limited to 'src/main/scala/firrtl/LoweringCompilers.scala')
| -rw-r--r-- | src/main/scala/firrtl/LoweringCompilers.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/scala/firrtl/LoweringCompilers.scala b/src/main/scala/firrtl/LoweringCompilers.scala index c8430d2b..4d40d9a8 100644 --- a/src/main/scala/firrtl/LoweringCompilers.scala +++ b/src/main/scala/firrtl/LoweringCompilers.scala @@ -124,7 +124,6 @@ class HighFirrtlToMiddleFirrtl () extends Transform with SimpleRun { // TODO(izraelevitz): Create RenameMap from RemoveCHIRRTL class MiddleFirrtlToLowFirrtl () extends Transform with SimpleRun { val passSeq = Seq( - passes.Legalize, passes.LowerTypes, passes.ResolveKinds, passes.InferTypes, @@ -146,6 +145,7 @@ class EmitVerilogFromLowFirrtl (val writer: Writer) extends Transform with Simpl passes.ConstProp, passes.PadWidths, passes.ConstProp, + passes.Legalize, passes.VerilogWrap, passes.SplitExpressions, passes.CommonSubexpressionElimination, |