From 9edf656e11084958d9e90807a4740a57b83babfe Mon Sep 17 00:00:00 2001
From: Jack
Date: Wed, 18 May 2016 12:02:52 -0700
Subject: Legalize bit select. Run Legalize after PadWidths.

Bit selecting a literal resulted in invalid Verilog. Legalize now deals with
this by replacing any bits select of UInt or SInt literals with a new literal
composed of the selected bits. Legalize also is now run after PadWidths because
that pass introduces this issue.

Fixes #170
---
 src/main/scala/firrtl/LoweringCompilers.scala | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/main/scala/firrtl/LoweringCompilers.scala')

diff --git a/src/main/scala/firrtl/LoweringCompilers.scala b/src/main/scala/firrtl/LoweringCompilers.scala
index c8430d2b..4d40d9a8 100644
--- a/src/main/scala/firrtl/LoweringCompilers.scala
+++ b/src/main/scala/firrtl/LoweringCompilers.scala
@@ -124,7 +124,6 @@ class HighFirrtlToMiddleFirrtl () extends Transform with SimpleRun {
 // TODO(izraelevitz): Create RenameMap from RemoveCHIRRTL
 class MiddleFirrtlToLowFirrtl () extends Transform with SimpleRun {
    val passSeq = Seq(
-      passes.Legalize,
       passes.LowerTypes,
       passes.ResolveKinds,
       passes.InferTypes,
@@ -146,6 +145,7 @@ class EmitVerilogFromLowFirrtl (val writer: Writer) extends Transform with Simpl
       passes.ConstProp,
       passes.PadWidths,
       passes.ConstProp,
+      passes.Legalize,
       passes.VerilogWrap,
       passes.SplitExpressions,
       passes.CommonSubexpressionElimination,
-- 
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