diff options
| author | albertchen-sifive | 2018-08-30 13:51:44 -0700 |
|---|---|---|
| committer | Jack Koenig | 2018-08-30 13:51:44 -0700 |
| commit | 8a4893dc6d9ce994ebbecfefe049e9f5cb8bd5b1 (patch) | |
| tree | dc59fd802b511f30c8ba68e5aaa935eaf412807f /src/main/scala/firrtl/Compiler.scala | |
| parent | a564d73f35703f8ba35b3e2c3263f1d9a65746fa (diff) | |
Emit Verilog Comments (#874)
add description nodes, transform; modify VerilogEmitter to emit comments
Diffstat (limited to 'src/main/scala/firrtl/Compiler.scala')
| -rw-r--r-- | src/main/scala/firrtl/Compiler.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/scala/firrtl/Compiler.scala b/src/main/scala/firrtl/Compiler.scala index b34782b5..9044c5a8 100644 --- a/src/main/scala/firrtl/Compiler.scala +++ b/src/main/scala/firrtl/Compiler.scala @@ -331,7 +331,7 @@ object CompilerUtils extends LazyLogging { /** Generates a sequence of [[Transform]]s to lower a Firrtl circuit * * @param inputForm [[CircuitForm]] to lower from - * @param outputForm [[CircuitForm to lower to + * @param outputForm [[CircuitForm]] to lower to * @return Sequence of transforms that will lower if outputForm is lower than inputForm */ def getLoweringTransforms(inputForm: CircuitForm, outputForm: CircuitForm): Seq[Transform] = { |