All of src/ formatted with scalafmt

1 files changed, 99 insertions, 76 deletions

diff --git a/src/main/scala/firrtl/Compiler.scala b/src/main/scala/firrtl/Compiler.scala
index db4853a2..ec09cace 100644
--- a/src/main/scala/firrtl/Compiler.scala
+++ b/src/main/scala/firrtl/Compiler.scala
@@ -13,7 +13,7 @@ import firrtl.annotations._
 import firrtl.ir.Circuit
 import firrtl.Utils.throwInternalError
 import firrtl.annotations.transforms.{EliminateTargetPaths, ResolvePaths}
-import firrtl.options.{DependencyAPI, Dependency, StageUtils, TransformLike}
+import firrtl.options.{Dependency, DependencyAPI, StageUtils, TransformLike}
 import firrtl.stage.Forms
 
 /** Container of all annotations for a Firrtl compiler */
@@ -34,19 +34,22 @@ object AnnotationSeq {
   *   Generally only a return value from [[Transform]]s
   */
 case class CircuitState(
-    circuit: Circuit,
-    form: CircuitForm,
-    annotations: AnnotationSeq,
-    renames: Option[RenameMap]) {
+  circuit:     Circuit,
+  form:        CircuitForm,
+  annotations: AnnotationSeq,
+  renames:     Option[RenameMap]) {
 
   /** Helper for getting just an emitted circuit */
   def emittedCircuitOption: Option[EmittedCircuit] =
-    emittedComponents collectFirst { case x: EmittedCircuit => x }
+    emittedComponents.collectFirst { case x: EmittedCircuit => x }
+
   /** Helper for getting an [[EmittedCircuit]] when it is known to exist */
   def getEmittedCircuit: EmittedCircuit = emittedCircuitOption match {
     case Some(emittedCircuit) => emittedCircuit
     case None =>
-      throw new FirrtlInternalException(s"No EmittedCircuit found! Did you delete any annotations?\n$deletedAnnotations")
+      throw new FirrtlInternalException(
+        s"No EmittedCircuit found! Did you delete any annotations?\n$deletedAnnotations"
+      )
   }
 
   /** Helper function for extracting emitted components from annotations */
@@ -64,7 +67,7 @@ case class CircuitState(
   def resolvePaths(targets: Seq[CompleteTarget]): CircuitState = targets match {
     case Nil => this
     case _ =>
-      val newCS = new EliminateTargetPaths().runTransform(this.copy(annotations = ResolvePaths(targets) +: annotations ))
+      val newCS = new EliminateTargetPaths().runTransform(this.copy(annotations = ResolvePaths(targets) +: annotations))
       newCS.copy(form = form)
   }
 
@@ -73,8 +76,8 @@ case class CircuitState(
     * @return
     */
   def resolvePathsOf(annoClasses: Class[_]*): CircuitState = {
-    val targets = getAnnotationsOf(annoClasses:_*).flatMap(_.getTargets)
-    if(targets.nonEmpty) resolvePaths(targets.flatMap{_.getComplete}) else this
+    val targets = getAnnotationsOf(annoClasses: _*).flatMap(_.getTargets)
+    if (targets.nonEmpty) resolvePaths(targets.flatMap { _.getComplete }) else this
   }
 
   /** Returns all annotations which are of a class in annoClasses
@@ -105,7 +108,8 @@ object CircuitState {
   */
 @deprecated(
   "Mix-in the DependencyAPIMigration trait into your Transform and specify its Dependency API dependencies. See: https://bit.ly/2Voppre",
-  "FIRRTL 1.3")
+  "FIRRTL 1.3"
+)
 sealed abstract class CircuitForm(private val value: Int) extends Ordered[CircuitForm] {
   // Note that value is used only to allow comparisons
   def compare(that: CircuitForm): Int = this.value - that.value
@@ -125,7 +129,8 @@ sealed abstract class CircuitForm(private val value: Int) extends Ordered[Circui
   */
 @deprecated(
   "Mix-in the DependencyAPIMigration trait into your Transform and specify its Dependency API dependencies. See: https://bit.ly/2Voppre",
-  "FIRRTL 1.3")
+  "FIRRTL 1.3"
+)
 final case object ChirrtlForm extends CircuitForm(value = 3) {
   val outputSuffix: String = ".fir"
 }
@@ -139,7 +144,8 @@ final case object ChirrtlForm extends CircuitForm(value = 3) {
   */
 @deprecated(
   "Mix-in the DependencyAPIMigration trait into your Transform and specify its Dependency API dependencies. See: https://bit.ly/2Voppre",
-  "FIRRTL 1.3")
+  "FIRRTL 1.3"
+)
 final case object HighForm extends CircuitForm(2) {
   val outputSuffix: String = ".hi.fir"
 }
@@ -153,7 +159,8 @@ final case object HighForm extends CircuitForm(2) {
   */
 @deprecated(
   "Mix-in the DependencyAPIMigration trait into your Transform and specify its Dependency API dependencies. See: https://bit.ly/2Voppre",
-  "FIRRTL 1.3")
+  "FIRRTL 1.3"
+)
 final case object MidForm extends CircuitForm(1) {
   val outputSuffix: String = ".mid.fir"
 }
@@ -166,7 +173,8 @@ final case object MidForm extends CircuitForm(1) {
   */
 @deprecated(
   "Mix-in the DependencyAPIMigration trait into your Transform and specify its Dependency API dependencies. See: https://bit.ly/2Voppre",
-  "FIRRTL 1.3")
+  "FIRRTL 1.3"
+)
 final case object LowForm extends CircuitForm(0) {
   val outputSuffix: String = ".lo.fir"
 }
@@ -184,7 +192,8 @@ final case object LowForm extends CircuitForm(0) {
   */
 @deprecated(
   "Mix-in the DependencyAPIMigration trait into your Transform and specify its Dependency API dependencies. See: https://bit.ly/2Voppre",
-  "FIRRTL 1.3")
+  "FIRRTL 1.3"
+)
 final case object UnknownForm extends CircuitForm(-1) {
   override def compare(that: CircuitForm): Int = { sys.error("Illegal to compare UnknownForm"); 0 }
 
@@ -212,12 +221,15 @@ private[firrtl] object Transform {
     logger.info(s"Form: ${after.form}")
     logger.trace(s"Annotations:")
     logger.trace {
-      JsonProtocol.serializeTry(remappedAnnotations).recoverWith {
-        case NonFatal(e) =>
-          val msg = s"Exception thrown during Annotation serialization:\n  " +
-                    e.toString.replaceAll("\n", "\n  ")
-          Try(msg)
-      }.get
+      JsonProtocol
+        .serializeTry(remappedAnnotations)
+        .recoverWith {
+          case NonFatal(e) =>
+            val msg = s"Exception thrown during Annotation serialization:\n  " +
+              e.toString.replaceAll("\n", "\n  ")
+            Try(msg)
+        }
+        .get
     }
 
     logger.trace(s"Circuit:\n${after.circuit.serialize}")
@@ -234,17 +246,18 @@ private[firrtl] object Transform {
     * @return the updated annotations
     */
   def propagateAnnotations(
-      name: String,
-      logger: Logger,
-      inAnno: AnnotationSeq,
-      resAnno: AnnotationSeq,
-      renameOpt: Option[RenameMap]): AnnotationSeq = {
+    name:      String,
+    logger:    Logger,
+    inAnno:    AnnotationSeq,
+    resAnno:   AnnotationSeq,
+    renameOpt: Option[RenameMap]
+  ): AnnotationSeq = {
     val newAnnotations = {
       val inSet = mutable.LinkedHashSet() ++ inAnno
       val resSet = mutable.LinkedHashSet() ++ resAnno
       val deleted = (inSet -- resSet).map {
         case DeletedAnnotation(xFormName, delAnno) => DeletedAnnotation(s"$xFormName+$name", delAnno)
-        case anno => DeletedAnnotation(name, anno)
+        case anno                                  => DeletedAnnotation(name, anno)
       }
       val created = resSet -- inSet
       val unchanged = resSet & inSet
@@ -260,7 +273,7 @@ private[firrtl] object Transform {
       remappedAnnos.foreach { remapped =>
         val set = remapped2original.getOrElseUpdate(remapped, mutable.LinkedHashSet.empty[Annotation])
         set += anno
-        if(set.size > 1) keysOfNote += remapped
+        if (set.size > 1) keysOfNote += remapped
       }
       remappedAnnos
     }.toSeq
@@ -280,15 +293,11 @@ trait Transform extends TransformLike[CircuitState] with DependencyAPI[Transform
   def name: String = this.getClass.getName
 
   /** The [[firrtl.CircuitForm]] that this transform requires to operate on */
-  @deprecated(
-    "Use Dependency API methods for equivalent functionality. See: https://bit.ly/2Voppre",
-    "FIRRTL 1.3")
+  @deprecated("Use Dependency API methods for equivalent functionality. See: https://bit.ly/2Voppre", "FIRRTL 1.3")
   def inputForm: CircuitForm
 
   /** The [[firrtl.CircuitForm]] that this transform outputs */
-  @deprecated(
-    "Use Dependency API methods for equivalent functionality. See: https://bit.ly/2Voppre",
-    "FIRRTL 1.3")
+  @deprecated("Use Dependency API methods for equivalent functionality. See: https://bit.ly/2Voppre", "FIRRTL 1.3")
   def outputForm: CircuitForm
 
   /** Perform the transform, encode renaming with RenameMap, and can
@@ -324,8 +333,9 @@ trait Transform extends TransformLike[CircuitState] with DependencyAPI[Transform
       Dependency[SystemVerilogEmitter] :: Nil
 
     val emitters = inputForm match {
-      case C => Dependency[ChirrtlEmitter]      :: Dependency[HighFirrtlEmitter]   :: Dependency[MiddleFirrtlEmitter] :: lowEmitters
-      case H => Dependency[HighFirrtlEmitter]   :: Dependency[MiddleFirrtlEmitter] :: lowEmitters
+      case C =>
+        Dependency[ChirrtlEmitter] :: Dependency[HighFirrtlEmitter] :: Dependency[MiddleFirrtlEmitter] :: lowEmitters
+      case H => Dependency[HighFirrtlEmitter] :: Dependency[MiddleFirrtlEmitter] :: lowEmitters
       case M => Dependency[MiddleFirrtlEmitter] :: lowEmitters
       case L => lowEmitters
       case U => Nil
@@ -334,9 +344,9 @@ trait Transform extends TransformLike[CircuitState] with DependencyAPI[Transform
     val selfDep = Dependency.fromTransform(this)
 
     inputForm match {
-      case C => (fullCompilerSet                           ++ emitters - selfDep).toSeq
-      case H => (fullCompilerSet -- Forms.Deduped          ++ emitters - selfDep).toSeq
-      case M => (fullCompilerSet -- Forms.MidForm          ++ emitters - selfDep).toSeq
+      case C => (fullCompilerSet ++ emitters - selfDep).toSeq
+      case H => (fullCompilerSet -- Forms.Deduped ++ emitters - selfDep).toSeq
+      case M => (fullCompilerSet -- Forms.MidForm ++ emitters - selfDep).toSeq
       case L => (fullCompilerSet -- Forms.LowFormOptimized ++ emitters - selfDep).toSeq
       case U => Nil
     }
@@ -347,9 +357,9 @@ trait Transform extends TransformLike[CircuitState] with DependencyAPI[Transform
 
   override def invalidates(a: Transform): Boolean = {
     (inputForm, outputForm) match {
-      case (U, _) | (_, U)  => true  // invalidate everything
+      case (U, _) | (_, U)  => true // invalidate everything
       case (i, o) if i >= o => false // invalidate nothing
-      case (_, C)           => true  // invalidate everything
+      case (_, C)           => true // invalidate everything
       case (_, H)           => highOutputInvalidates(Dependency.fromTransform(a))
       case (_, M)           => midOutputInvalidates(Dependency.fromTransform(a))
       case (_, L)           => false // invalidate nothing
@@ -386,7 +396,7 @@ abstract class SeqTransform extends Transform with SeqTransformBased {
     /*
     require(state.form <= inputForm,
       s"[$name]: Input form must be lower or equal to $inputForm. Got ${state.form}")
-    */
+     */
     val ret = runTransforms(state)
     CircuitState(ret.circuit, outputForm, ret.annotations, ret.renames)
   }
@@ -401,7 +411,7 @@ trait ResolvedAnnotationPaths {
   val annotationClasses: Traversable[Class[_]]
 
   override def prepare(state: CircuitState): CircuitState = {
-    state.resolvePathsOf(annotationClasses.toSeq:_*)
+    state.resolvePathsOf(annotationClasses.toSeq: _*)
   }
 }
 
@@ -419,6 +429,7 @@ trait Emitter extends Transform {
 
 @deprecated("This will be removed in 1.4", "FIRRTL 1.3")
 object CompilerUtils extends LazyLogging {
+
   /** Generates a sequence of [[Transform]]s to lower a Firrtl circuit
     *
     * @param inputForm [[CircuitForm]] to lower from
@@ -427,7 +438,8 @@ object CompilerUtils extends LazyLogging {
     */
   @deprecated(
     "Use a TransformManager requesting which transforms you want to run. This will be removed in 1.4.",
-    "FIRRTL 1.3")
+    "FIRRTL 1.3"
+  )
   def getLoweringTransforms(inputForm: CircuitForm, outputForm: CircuitForm): Seq[Transform] = {
     // If outputForm is equal-to or higher than inputForm, nothing to lower
     if (outputForm >= inputForm) {
@@ -437,10 +449,15 @@ object CompilerUtils extends LazyLogging {
         case ChirrtlForm =>
           Seq(new ChirrtlToHighFirrtl) ++ getLoweringTransforms(HighForm, outputForm)
         case HighForm =>
-          Seq(new IRToWorkingIR, new ResolveAndCheck, new firrtl.transforms.DedupModules, new HighFirrtlToMiddleFirrtl) ++
+          Seq(
+            new IRToWorkingIR,
+            new ResolveAndCheck,
+            new firrtl.transforms.DedupModules,
+            new HighFirrtlToMiddleFirrtl
+          ) ++
             getLoweringTransforms(MidForm, outputForm)
-        case MidForm => Seq(new MiddleFirrtlToLowFirrtl) ++ getLoweringTransforms(LowForm, outputForm)
-        case LowForm => throwInternalError("getLoweringTransforms - LowForm") // should be caught by if above
+        case MidForm     => Seq(new MiddleFirrtlToLowFirrtl) ++ getLoweringTransforms(LowForm, outputForm)
+        case LowForm     => throwInternalError("getLoweringTransforms - LowForm") // should be caught by if above
         case UnknownForm => throwInternalError("getLoweringTransforms - UnknownForm") // should be caught by if above
       }
     }
@@ -479,28 +496,32 @@ object CompilerUtils extends LazyLogging {
     */
   @deprecated(
     "Use a TransformManager requesting which transforms you want to run. This will be removed in 1.4.",
-    "FIRRTL 1.3")
+    "FIRRTL 1.3"
+  )
   def mergeTransforms(lowering: Seq[Transform], custom: Seq[Transform]): Seq[Transform] = {
-    custom
-      .sortWith{
-        case (a, b) => (a, b) match {
+    custom.sortWith {
+      case (a, b) =>
+        (a, b) match {
           case (_: Emitter, _: Emitter) => false
-          case (_, _: Emitter)          => true
-          case _                        => false }}
-      .foldLeft(lowering) { case (transforms, xform) =>
-      val index = transforms lastIndexWhere (_.outputForm == xform.inputForm)
-      assert(index >= 0 || xform.inputForm == ChirrtlForm, // If ChirrtlForm just put at front
-        s"No transform in $lowering has outputForm ${xform.inputForm} as required by $xform")
-      val (front, back) = transforms.splitAt(index + 1) // +1 because we want to be AFTER index
-      front ++ List(xform) ++ getLoweringTransforms(xform.outputForm, xform.inputForm) ++ back
+          case (_, _: Emitter) => true
+          case _ => false
+        }
     }
+      .foldLeft(lowering) {
+        case (transforms, xform) =>
+          val index = transforms.lastIndexWhere(_.outputForm == xform.inputForm)
+          assert(
+            index >= 0 || xform.inputForm == ChirrtlForm, // If ChirrtlForm just put at front
+            s"No transform in $lowering has outputForm ${xform.inputForm} as required by $xform"
+          )
+          val (front, back) = transforms.splitAt(index + 1) // +1 because we want to be AFTER index
+          front ++ List(xform) ++ getLoweringTransforms(xform.outputForm, xform.inputForm) ++ back
+      }
   }
 
 }
 
-@deprecated(
-  "Migrate to firrtl.stage.transforms.Compiler. This will be removed in 1.4.",
-  "FIRRTL 1.3")
+@deprecated("Migrate to firrtl.stage.transforms.Compiler. This will be removed in 1.4.", "FIRRTL 1.3")
 trait Compiler extends Transform with DependencyAPIMigration {
   def emitter: Emitter
 
@@ -511,15 +532,17 @@ trait Compiler extends Transform with DependencyAPIMigration {
   def transforms: Seq[Transform]
 
   final override def execute(state: CircuitState): CircuitState =
-    new stage.transforms.Compiler (
+    new stage.transforms.Compiler(
       targets = (transforms :+ emitter).map(Dependency.fromTransform),
       currentState = prerequisites,
       knownObjects = (transforms :+ emitter).toSet
     ).execute(state)
 
-  require(transforms.size >= 1,
-          s"Compiler transforms for '${this.getClass.getName}' must have at least ONE Transform! " +
-            "Use IdentityTransform if you need an identity/no-op transform.")
+  require(
+    transforms.size >= 1,
+    s"Compiler transforms for '${this.getClass.getName}' must have at least ONE Transform! " +
+      "Use IdentityTransform if you need an identity/no-op transform."
+  )
 
   /** Perform compilation
     *
@@ -531,10 +554,9 @@ trait Compiler extends Transform with DependencyAPIMigration {
   @deprecated(
     "Migrate to '(new FirrtlStage).execute(args: Array[String], annotations: AnnotationSeq)'." +
       "This will be removed in 1.4.",
-    "FIRRTL 1.0")
-  def compile(state: CircuitState,
-              writer: Writer,
-              customTransforms: Seq[Transform] = Seq.empty): CircuitState = {
+    "FIRRTL 1.0"
+  )
+  def compile(state: CircuitState, writer: Writer, customTransforms: Seq[Transform] = Seq.empty): CircuitState = {
     val finalState = compileAndEmit(state, customTransforms)
     writer.write(finalState.getEmittedCircuit.value)
     finalState
@@ -555,9 +577,9 @@ trait Compiler extends Transform with DependencyAPIMigration {
   @deprecated(
     "Migrate to '(new FirrtlStage).execute(args: Array[String], annotations: AnnotationSeq)'." +
       "This will be removed in 1.4.",
-    "FIRRTL 1.3.3")
-  def compileAndEmit(state: CircuitState,
-                     customTransforms: Seq[Transform] = Seq.empty): CircuitState = {
+    "FIRRTL 1.3.3"
+  )
+  def compileAndEmit(state: CircuitState, customTransforms: Seq[Transform] = Seq.empty): CircuitState = {
     val emitAnno = EmitCircuitAnnotation(emitter.getClass)
     compile(state.copy(annotations = emitAnno +: state.annotations), emitter +: customTransforms)
   }
@@ -574,9 +596,10 @@ trait Compiler extends Transform with DependencyAPIMigration {
   @deprecated(
     "Migrate to '(new FirrtlStage).execute(args: Array[String], annotations: AnnotationSeq)'." +
       "This will be removed in 1.4.",
-    "FIRRTL 1.3.3")
+    "FIRRTL 1.3.3"
+  )
   def compile(state: CircuitState, customTransforms: Seq[Transform]): CircuitState = {
-    val transformManager = new stage.transforms.Compiler (
+    val transformManager = new stage.transforms.Compiler(
       targets = (emitter +: customTransforms ++: transforms).map(Dependency.fromTransform),
       currentState = prerequisites,
       knownObjects = (transforms :+ emitter).toSet