diff options
| author | Schuyler Eldridge | 2019-02-22 17:45:26 -0500 |
|---|---|---|
| committer | Schuyler Eldridge | 2019-02-25 00:16:25 -0500 |
| commit | 5decb4079814be1fef10a02bf5518ec4e29f37dd (patch) | |
| tree | 8a827aa0830adaa4dde8fef8185987a64938ffc1 /src/main/scala/firrtl/AddDescriptionNodes.scala | |
| parent | 5608aa8f42c1d69b59bee158d14fc6cef9b19a47 (diff) | |
Fix almost all Scaladoc warnings
This fixes all Scaladoc warnings except for those trying to link to
Java.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Diffstat (limited to 'src/main/scala/firrtl/AddDescriptionNodes.scala')
| -rw-r--r-- | src/main/scala/firrtl/AddDescriptionNodes.scala | 7 |
1 files changed, 3 insertions, 4 deletions
diff --git a/src/main/scala/firrtl/AddDescriptionNodes.scala b/src/main/scala/firrtl/AddDescriptionNodes.scala index 1ed3259f..2cd8b9f7 100644 --- a/src/main/scala/firrtl/AddDescriptionNodes.scala +++ b/src/main/scala/firrtl/AddDescriptionNodes.scala @@ -60,10 +60,9 @@ private case class DescribedMod(description: Description, def foreachInfo(f: Info => Unit): Unit = mod.foreachInfo(f) } -/** Wraps modules or statements with their respective described nodes. - * Descriptions come from [[DescriptionAnnotation]]. Describing a - * module or any of its ports will turn it into a [[DescribedMod]]. - * Describing a Statement will turn it into a [[DescribedStmt]] +/** Wraps modules or statements with their respective described nodes. Descriptions come from [[DescriptionAnnotation]]. + * Describing a module or any of its ports will turn it into a `DescribedMod`. Describing a Statement will turn it into + * a (private) `DescribedStmt`. * * @note should only be used by VerilogEmitter, described nodes will * break other transforms. |
