aboutsummaryrefslogtreecommitdiff
path: root/src/main/antlr4
diff options
context:
space:
mode:
authorjackkoenig2016-09-22 19:10:40 -0700
committerJack Koenig2016-10-26 15:15:37 -0700
commit4b8a0d2af52ceeb3ff5d05082af53bac76744361 (patch)
tree3c416fe2532c504cff18efc8b6d0dccab207802a /src/main/antlr4
parente25c6f7a5e4e1bfbfcb8345288be478caa469525 (diff)
Add Support for Parameterized ExtModules and Name Override
Adds support for Integer, Double/Real, and String parameters in external modules. Also add name field to extmodules so that emitted name can be different from Firrtl name. This is important because parameterized extmodules will frequently have differing IO even though they need to be emitted as instantiating the same Verilog module.
Diffstat (limited to 'src/main/antlr4')
-rw-r--r--src/main/antlr4/FIRRTL.g416
1 files changed, 15 insertions, 1 deletions
diff --git a/src/main/antlr4/FIRRTL.g4 b/src/main/antlr4/FIRRTL.g4
index 4ceed9f0..f4d9d3f8 100644
--- a/src/main/antlr4/FIRRTL.g4
+++ b/src/main/antlr4/FIRRTL.g4
@@ -63,7 +63,7 @@ circuit
module
: 'module' id ':' info? INDENT port* moduleBlock DEDENT
- | 'extmodule' id ':' info? INDENT port* DEDENT
+ | 'extmodule' id ':' info? INDENT port* defname? parameter* DEDENT
;
port
@@ -89,6 +89,16 @@ field
: 'flip'? id ':' type
;
+defname
+ : 'defname' '=' id NEWLINE
+ ;
+
+parameter
+ : 'parameter' id '=' IntLit NEWLINE
+ | 'parameter' id '=' StringLit NEWLINE
+ | 'parameter' id '=' DoubleLit NEWLINE
+ ;
+
moduleBlock
: simple_stmt*
;
@@ -291,6 +301,10 @@ IntLit
| '"' 'h' ( HexDigit )+ '"'
;
+DoubleLit
+ : ( '+' | '-' )? Digit+ '.' Digit+ ( 'E' Digit+ )?
+ ;
+
fragment
Nondigit
: [a-zA-Z_]