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| author | Albert Magyar | 2020-06-25 13:05:52 -0700 |
|---|---|---|
| committer | Albert Magyar | 2020-06-26 11:08:42 -0700 |
| commit | fe7754a4ef92b2333f43458e53478e29cedad1c7 (patch) | |
| tree | 59a4e3a65af49bf641ce5929a69eb0bd61d7acdc /scripts | |
| parent | 87c5d034f2d32132eed01a6f43b567af9b34cbcd (diff) | |
Add ConvertAsserts transform to map asserts to Verilog-friendly nodes
* ConvertAsserts maps each assert into a gated print-and-stop
* ConvertAsserts is an optional prereq of RemoveVerificationStatements
* ConvertAsserts generates Low FIRRTL
* Drop print for asserts that have an empty message
* Fix scaladoc formatting from review
Co-authored-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Diffstat (limited to 'scripts')
0 files changed, 0 insertions, 0 deletions