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| author | Schuyler Eldridge | 2020-05-01 15:07:54 -0400 |
|---|---|---|
| committer | GitHub | 2020-05-01 19:07:54 +0000 |
| commit | ee0d4079c6076b0af1f9e557f69e7346cdd89d4f (patch) | |
| tree | 8e56e51ba311c5ba9e5eb935c810cf5bb4a9eb64 /scripts | |
| parent | 3b4e691bc4720e56089f424dbf5cb70403c1babc (diff) | |
Add missing invalidations to some transforms (#1541)
This adds missing invalidations to four transforms:
- ExpandConnects
- RemoveAccesses
- SplitExpressions
- VerilogMemDelays
This necessarily updates test cases which expect exact transform
orders to reflect the new order.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
Diffstat (limited to 'scripts')
0 files changed, 0 insertions, 0 deletions