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| author | Fabian Schuiki | 2021-04-16 16:18:32 +0200 |
|---|---|---|
| committer | GitHub | 2021-04-16 14:18:32 +0000 |
| commit | e9b2946c962f91a04611e32b1a9d03f78e7edf2b (patch) | |
| tree | 20f2ff423691446e3fcfcab5ce630ab2923b3c8c /scripts | |
| parent | fc86112bc09f3e804d76e329fea96acb70e4909d (diff) | |
Fix signedness of xor const prop with zero (#2179)
Constant propagation of the Xor op folds `xor(a, SInt(0))` to
`asUInt(a)`. For comparison, Or folds to `asUInt(pad(a, W))`. This can
be a problem in the following case:
circuit Foo :
module Foo :
input a: UInt<3>
output b: UInt<4>
b <= asUInt(xor(asSInt(a), SInt<4>(0)))
This would emit the assignment as `b = a` instead of the sign-extended
`b = {{1{a[2]}},a}`.
This requires adjusting the `pad(e, t)` function use in const prop,
which currently just inserts a `Pad` prim op with the requested output
type. However, the function advertises that it pads *to the width* of
the type `t`. Some of the folds rely on this and request the padding of
a SInt<N> to the width of a UInt<M>. But the current implementation then
then actually returns a `Pad` op with type UInt<M>, instead of the
SInt<M> that was requested.
Diffstat (limited to 'scripts')
0 files changed, 0 insertions, 0 deletions
