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| author | Andrew Waterman | 2019-03-26 12:11:35 -0700 |
|---|---|---|
| committer | Andrew Waterman | 2019-03-26 12:12:37 -0700 |
| commit | a076a8ec18bdda6f8a964bea7f91d32cb17f0b89 (patch) | |
| tree | 670e710046e4b522ec7b7ed7f49bcb0e4fa36c9c /scripts | |
| parent | ed7c8409d772964dba81de7d2076bc1aeb43c58e (diff) | |
DCE printf and stop statements with constant-0 enables
This gets rid of about 10% of the generated Verilog in the rocket-chip
default config.
Diffstat (limited to 'scripts')
0 files changed, 0 insertions, 0 deletions