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| author | Jack Koenig | 2018-05-15 11:29:43 -0700 |
|---|---|---|
| committer | GitHub | 2018-05-15 11:29:43 -0700 |
| commit | 84b5fc1bc97e014bc03056a3f752c40ec6100701 (patch) | |
| tree | 2af78be6b61fbb82c1261d3d30ab9cabbcf401f4 /scripts | |
| parent | abcb22d6c34eb51749e7bc848b437a165bc5b330 (diff) | |
Replace truncating add and sub with addw/subw (#800)
Replaces old VerilogWrap which didn't work with split expressions and was
actually buggy anyway. This functionality reduces unnecessary intermediates in
emitted Verilog.
Diffstat (limited to 'scripts')
0 files changed, 0 insertions, 0 deletions