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| author | Schuyler Eldridge | 2020-08-01 13:01:44 -0400 |
|---|---|---|
| committer | GitHub | 2020-08-01 17:01:44 +0000 |
| commit | 687f3ddbbcd9217542a4bc0e2c256559d2c67a5b (patch) | |
| tree | 056f4ef5c9f3aabf370599264a47f8831f8d8722 /scripts | |
| parent | a82958714c096eefebde16e0491b978135c1757e (diff) | |
Error on ExtModules w/ same defname, diff. ports (#1734)
* Use signed output in LargeParamExecutionTest
Change the Verilog used in LargeParamExecutionTest to match its
ExtModule specification. An ExtModule with an SInt port should map to
a separate Verilog module with a signed port and this is disjoint from
an ExtModule with a UInt port.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
* Error on ExtModules w/ same defname, diff. ports
Adds a high form check to ensure that external modules that have the
same defname also have exactly the same ports.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
Diffstat (limited to 'scripts')
0 files changed, 0 insertions, 0 deletions