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| author | Andrew Waterman | 2019-01-23 13:27:19 -0800 |
|---|---|---|
| committer | Adam Izraelevitz | 2019-01-23 13:27:19 -0800 |
| commit | 1738c1ef0ac95fae25d52586b3b0348de80de2ff (patch) | |
| tree | e28d770a8ad05b7f9635365248ee6a44a766714e /scripts | |
| parent | df3c3fb5eedd3e2ac95b9f210268e4e515d6344c (diff) | |
Improve Shl codegen; eliminate Shlw WIR node (#994)
* Improve Shl codegen; eliminate Shlw WIR node
If we emit shl(x, k) as {x, k'h0} instead of (x << k), then there's
no need for Verilog-specific padding in the PadWidths pass. Avoiding
the redundant padding improves compiler/simulator performance and
renders Shlw unnecessary.
* [skip formal checks] Add test
Diffstat (limited to 'scripts')
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