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| author | Carlos Eduardo | 2021-03-09 15:49:37 -0300 |
|---|---|---|
| committer | GitHub | 2021-03-09 18:49:37 +0000 |
| commit | efdefde2a5fa13de8faa8c141f852391909225df (patch) | |
| tree | f9b16501a688feedc8bcebff611148bc12f39de3 /scripts/parse_firrtl_transform_log.py | |
| parent | 8a4c156f401c8bfab5f2d595c32c20534f0722d7 (diff) | |
Create annotation to allow inline readmem in Verilog (#2107)
This PR adds a new annotation allowing inline loading for memory files
in Verilog code.
Diffstat (limited to 'scripts/parse_firrtl_transform_log.py')
0 files changed, 0 insertions, 0 deletions