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| author | Albert Magyar | 2021-03-09 21:30:53 -0800 |
|---|---|---|
| committer | Albert Magyar | 2021-04-05 12:00:02 -0700 |
| commit | a90cf1105467cab7c6708ea3faae35e1454cb0fd (patch) | |
| tree | bfc40443826cc44196230f7427aa5ba80ca8f332 /scripts/parse_firrtl_transform_log.py | |
| parent | 088c82244d58d7e5c8a6ad6e7e3bb1edaf81af3a (diff) | |
Allow direct emission of sync-read memories to Verilog
* Emit readwrite ports, if applicable
* Does not change VerilogMemDelays -> no effect on default flow
* Use more single-line declare-and-assign statements for mem wires
* Update error messages for too-complex memories in VerilogEmitter
* Run scalafmt on VerilogEmitter
Diffstat (limited to 'scripts/parse_firrtl_transform_log.py')
0 files changed, 0 insertions, 0 deletions