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| author | Jack Koenig | 2020-05-01 12:58:43 -0700 |
|---|---|---|
| committer | Jack Koenig | 2020-05-04 13:25:54 -0700 |
| commit | 9624121164e0c65f7ce81048a8c0621882f1d55b (patch) | |
| tree | 3283fe625276b0dc4e0baa092affc8b2c785b7e5 /scripts/parse_firrtl_transform_log.py | |
| parent | ee0d4079c6076b0af1f9e557f69e7346cdd89d4f (diff) | |
Add LegalizeAndReductionsTransform
Workaround for https://github.com/verilator/verilator #2300
present in Verilator versions v4.026 - v4.032. This transform turns AND
reductions for expressions > 64-bits into an equality check with all
ones. It is included as a prerequisite for all Verilog emitters.
Diffstat (limited to 'scripts/parse_firrtl_transform_log.py')
0 files changed, 0 insertions, 0 deletions