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| author | Kevin Laeufer | 2021-08-09 13:29:52 -0700 |
|---|---|---|
| committer | GitHub | 2021-08-09 20:29:52 +0000 |
| commit | 6e7982ba015f5e8b3e1d17086c7abe4eaf04458e (patch) | |
| tree | c4d4b7a81ca8b59b4a102f0e98f63183c02594b0 /scripts/parse_firrtl_transform_log.py | |
| parent | 5f6ad34dcc6a74d44e63d56d3510bb56f43c5df1 (diff) | |
PropagatePresetAnnotations: remove false prerequisites (#2323)
The SMT backend actually needs to run PropagatePresetAnnotations
(as will treadle at some point).
None of the Verilog specific passes were actually required!
Diffstat (limited to 'scripts/parse_firrtl_transform_log.py')
0 files changed, 0 insertions, 0 deletions