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authorSchuyler Eldridge2021-01-19 22:49:31 -0500
committerGitHub2021-01-20 03:49:31 +0000
commit698a9dca52f819aca6309e3b03f2420a71bc89a6 (patch)
tree4e7afa7beec5a176bd65922a5d29a334486b774e /scripts/parse_firrtl_transform_log.py
parent6d8e9041e000f9ea5fb3d069d1f9ec06d2158575 (diff)
Add --dont-fold option to disable folding prim ops (#2040)
This adds a --dont-fold options (backed by a DisableFold annotation) that lets a user specify primitive operations which should never be folded. This feature lets a user disable certain folds which may be allowable in FIRRTL (or by any sane synthesis tool), but due to inane Verilog language design causes formal equivalence tools to fail due to the fold. Add a test that a user can disable `a / a -> 1` with a DisableFold(PrimOps.Div) annotation. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
Diffstat (limited to 'scripts/parse_firrtl_transform_log.py')
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