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| author | Schuyler Eldridge | 2021-10-04 22:24:51 -0400 |
|---|---|---|
| committer | Schuyler Eldridge | 2021-10-04 22:24:51 -0400 |
| commit | 527eba4966513bcfd1453fd76cfb241272fe602c (patch) | |
| tree | b0bb1768492a7af1710ee66da048f0c62691d0ab /scripts/parse_firrtl_transform_log.py | |
| parent | 519e8c8dea592d2faf949a1a1aa49ea303bd1c72 (diff) | |
Hotfix for Vector Reg Init LegalizeConnects Bug
Add a private pass, LegalizeConnectsOnly, that behaves like
LegalizeConnects, but only pads connects instead of connects and
register inits. Padding is necessary for ReplSeqMem, but ReplSeqMem
runs before LowerTypes and vector registers can still exist at this
point. Connects, conversely, are all blown out by ExpandConnects and
can be safely, blindly treated as ground type.
Fixes #2379.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
Diffstat (limited to 'scripts/parse_firrtl_transform_log.py')
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