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| author | Jack Koenig | 2021-06-22 09:52:53 -0700 |
|---|---|---|
| committer | GitHub | 2021-06-22 09:52:53 -0700 |
| commit | 11128d93ea5412508b2616fda862abf05a59b435 (patch) | |
| tree | b49535602228ced1d4891c675b9f3021dad144ea /scripts/parse_firrtl_transform_log.py | |
| parent | ef4d9fc765ec1ccd336104c72bce7659bc9f4b64 (diff) | |
Fix VerilogMemDelays use before declaration (#2278)
The pass injects pipe registers immediately after the declaration of the
memory. This can be problematic if the clock for the associated memory
port is defined after the declaration of the memory. For any memory port
clocks that are driven by non-ports, we now inject a wire before the
pipe register declarations to be sure there are no
use-before-declaration issues.
Diffstat (limited to 'scripts/parse_firrtl_transform_log.py')
0 files changed, 0 insertions, 0 deletions