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| author | Albert Chen | 2018-11-15 08:53:16 -0800 |
|---|---|---|
| committer | Schuyler Eldridge | 2018-11-15 08:53:16 -0800 |
| commit | b90589f5cd9d4048ada2a05d5225874791546170 (patch) | |
| tree | 126699d5955746ecb7e4d5432299c648ec3446d5 /project | |
| parent | 6ece732d09b8610ae50545dab312d6759ac2f8e2 (diff) | |
Combine cats (#851)
- Add firrtl.transforms.CombineCats
- Use CombineCats in LowFirrtlOptimization
- Modify Verilog emitter to allow for nested Cat DoPrims
- Modify firrtlEquivalenceTest to write input FIRRTL string to test directory
Diffstat (limited to 'project')
0 files changed, 0 insertions, 0 deletions