diff options
| author | sinofp | 2021-05-22 15:16:32 +0800 |
|---|---|---|
| committer | GitHub | 2021-05-22 07:16:32 +0000 |
| commit | 8bca41522cdc4b8ff69734cd159ce29f984d3290 (patch) | |
| tree | cf6d43e872ca40dae86a5e9b8ceca118242c28ca /project | |
| parent | 117b84a15a352451c1217155f96b09d098681baf (diff) | |
Rewrite vlsi_mem_gen into a Firrtl Transform (#2202)
* Add GenVerilogMemBehaviorModelAnno & vlsiMemGen
* Add CLI support for GenVerilogMemBehaviorModelAnno
* Add simple test for GenVerilogMemBehaviorModelAnno
* Fix for review
1. rename case class Port(prefix, `type`) to Port(prefix, portType)
2. fix AnnotatedMemoriesAnnotation collect function.
3. fix bug that ModuleName is not correct.
* Format DumpMemoryAnnotations & ReplSeqMemTests
* Fix for review
1. Inline genDecl, genPortSpec, genSequential, genCombinational
2. Add DefAnnotatedMemory informations in header
3. Change helpText
4. Check output Verilog by Verilator, the code is from FirrtlRunners#lintVerilog
* Fix ReadWritePort mask name
Co-authored-by: Jiuyang Liu <liu@jiuyang.me>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
Diffstat (limited to 'project')
0 files changed, 0 insertions, 0 deletions