Added chisel feedback to firrtl spec. Datapath_new triggers too large a width error

1 files changed, 8 insertions, 0 deletions

diff --git a/notes/chisel-feedback-7.6.15.txt b/notes/chisel-feedback-7.6.15.txt
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+Firrtl spec feedback
+
+add limited support for zero width wires?
+
+Add more explanation for what types of passes
+spec of what chisel3/firrtl whole compiler toolchain looks like
+
+Why is verilog generation unreadable and slow for chisel 2.0?