Finished expand accessors and lower to ground

3 files changed, 84 insertions, 0 deletions

diff --git a/notes/notes.03.16.15.txt b/notes/notes.03.16.15.txt
new file mode 100644
index 00000000..d017a015
--- /dev/null
+++ b/notes/notes.03.16.15.txt
@@ -0,0 +1,24 @@
+Why did we remove the letrec?
+
+Why was it there? A way to express all the enables and input values without the need for the when statement, and also allows you to analyze the graph without worrying about last connect semantics, and allows you to analyze the graph without worrying about compound datatypes, known widths, known genders.
+
+Now we have a way to do it without this. We introduced the Register expression and read/writeport expressions, which enable you to declare them as a function of their inputs and enables. We expand all datatypes into their ground types. Lastly, we express the graph such that for every wire declaration, we ensure that there is only ever one connect to each wire.
+
+lowered form and higher form
+
+
+Add FIFOs to the IR - major semantics work.
+Write a pass expecting to be used on high firrtl, (in current firrtl it could break because we add new constructs) but is used on low firrtl.
+
+Front-end will write to special r.enable value that it will assign 1 to whenever r is written (or if a mem, read).
+
+Registers now have 2 fields, .data and .enable. Declare:
+reg r : { pckg : {enable} , valid}
+r.data := blah ; which has type {pckg : {enable, valid}}
+r.enable := UInt(1)
+bleh := r.data
+; no enable required
+
+Memories require enables on both reads and writes.
+
+
diff --git a/notes/notes.03.18.15.txt b/notes/notes.03.18.15.txt
new file mode 100644
index 00000000..7fdb1c3b
--- /dev/null
+++ b/notes/notes.03.18.15.txt
@@ -0,0 +1,52 @@
+WHEN EXPANSION
+
+Goal:
+reg r
+wire w
+when p1 :
+  w := b
+  r.init := x
+    when p2 :
+      w := c
+      r := d
+r := e
+
+==>
+
+1. Remove last connect semantics
+2. Remove conditional blocks
+3. Eliminate concept of scoping
+
+Exp    | Value
+--------------
+r      | e
+w      | mux(p1,mux(p2,c,b),null)
+r.init | mux(p1,x,null)
+
+==>
+
+Symbolic Value - what can appear in value column
+sv = e
+   | null
+   | svmux(e,sv1,sv2)
+
+State:
+{
+  r => void
+  r.init => p1
+  w => svmux(e,_,_)
+}
+
+==>
+
+Build two tables, one mapping symbols to symbolic values, and another mapping symbols to declared types
+
+if w is a wire:
+merge {r=>x, w=>y} with {r=>x} under p : {r=>svmux(p,x,x), w=>y}
+
+if s is a reg:
+merge {r=>x,s=>y} with {r=>x} under p : {r=>svmux(p,x,x), s=>svmux(p,y,void)}
+
+
+
+
diff --git a/notes/stanza-cheatsheet.txt b/notes/stanza-cheatsheet.txt
index 09342997..215fafbd 100644
--- a/notes/stanza-cheatsheet.txt
+++ b/notes/stanza-cheatsheet.txt
@@ -55,3 +55,11 @@ list(a) -> a
 list(a,b) -> a,b 
 
 println-all([a b c])
+
+to extract values (with correct type-age) from a tuple:
+val x = [1 "hi"]
+val [a,b] = x
+a typeof Int
+b typeof String
+
+to combine symbols: symbol-join