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| author | azidar | 2015-07-29 20:18:04 -0700 |
|---|---|---|
| committer | azidar | 2015-07-29 20:18:04 -0700 |
| commit | c442fe670afa4fc21c2c78f11a3957283a9b2391 (patch) | |
| tree | 3436e6ac582fad85f955f04aa2571b81033be45e /notes | |
| parent | 7646c2e3edf90ea13a83b76c97f35877263c5e63 (diff) | |
Updated frontend changes
Diffstat (limited to 'notes')
| -rw-r--r-- | notes/frontend-notes.04.16.15.txt | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/notes/frontend-notes.04.16.15.txt b/notes/frontend-notes.04.16.15.txt index fb7c1af9..7c571286 100644 --- a/notes/frontend-notes.04.16.15.txt +++ b/notes/frontend-notes.04.16.15.txt @@ -9,6 +9,14 @@ sub-wrap -> subw bit-and -> and bit-or -> or bit-xor -> xor +on-reset -> onreset +reg now has reset and clock +cmem/smem now has clock +accessor -> infer accessor +"Clock" is now a type, so the following declares a clock port: +module Queue : + input clk : Clock + ... |
