merge

3 files changed, 67 insertions, 4 deletions

diff --git a/notes/architecture.05.05.15.txt b/notes/architecture.05.05.15.txt
new file mode 100644
index 00000000..b66d663d
--- /dev/null
+++ b/notes/architecture.05.05.15.txt
@@ -0,0 +1,4 @@
+Omar/Ofar? wrote genesis and is Dave's boss
+Big problem is how to integrate different verilog, and put them all together to make it work
+   Can chisel help?
+Different clock domains? L2 should be in a different domain
diff --git a/notes/chisel.05.04.15.txt b/notes/chisel.05.04.15.txt
new file mode 100644
index 00000000..34ac637f
--- /dev/null
+++ b/notes/chisel.05.04.15.txt
@@ -0,0 +1,28 @@
+=========== FIRRTL PASSES ==============
+
+Parser : Parses text file and provides some error checking.
+   i: Parses the text file into an in-memory representation of the FIRRTL graph (tree).
+   +: Incorrect syntax correctly crashes the parser with an error message.
+   -: Error messages could be improved
+High Form Check : Ensures file has correct high firrtl form.
+   i: Ensures that initial file upholds various non-syntactic invariants
+   +: Some have been implemented. Current invariants not checked will likely crash the compiler in a later stage.
+   -: More to implemented (grunt work).
+Temp Elimination : Inline poorly-named single-assignment values.
+   ;Allows betterTo make the Chisel frontend simpler, we emit no nested expressions, and generate a lot of temps with non-intuitive names.
+Working IR : Replaces some IR nodes with working IR nodes with useful fields
+Make Explicit Reset : If not declared, reset is added to every module
+Resolve Kinds : Populates WRefs with the 'kind of reference'
+Infer Types : All type fields are inferred
+Type Check : All types are checked
+   -: Not implemented
+Resolve Genders : Genders of WRef and WAccessor is filled in
+Expand Accessors : Accessors to non-memory vectors are expanded to ConnectFromIndexed and ConnectToIndexed
+Lower To Ground : All types are lowered to ground types by expanding all Indexes and Subfields that are not instances
+Expand Indexed Connects : All ConnectFromIndexed and ConnectToIndexed are expanded to whens
+Expand Whens : Basic interpreter to calculate single assignment with muxes.
+Infer Widths : Width inferences
+Inline Instances
+Split Expressions : All nested expressions are expanded to single-assignment nodes with a relative name
+Real IR : All working IR nodes are removed
+To Flo : Flo is emitted
diff --git a/notes/primop-inference.txt b/notes/primop-inference.txt
index ec704ba6..7c1cd43b 100644
--- a/notes/primop-inference.txt
+++ b/notes/primop-inference.txt
@@ -1,3 +1,28 @@
+Support on-reset for now, but it will get deprecated. It was originally included to make it easier for the front-end to support Vec(Reg), but since this was a bad decision in Chisel, we shouldn't muddy up FIRRTL to compensate.
+   For now, we will add which of the reset signal for registers in their declaration, so on-reset will use that instead of the implicit reset
+Delete implicit reset, always make it explicit
+Clock will be a subtype of Port. Need to make sure it isn't used in any logic. It will be included in the declaration of registers.
+
+Primops - Different widths
+Backends will emit different things based on the type of the input arguments, and the widths.
+e.g.
+SInt<7> + SInt<4>
+For C++ : need to sign-extend SInt<4> and add to SInt<7>
+For Verilog : Emit as is, which will generate a 4-bit add and an increment circuit
+Verilog does not want it sign extended, so we should not ensure that widths should be different
+For backends that need strict width inference, you should write your own padding pass, and checking pass.
+
+Primops - Input Type dependence
+To simplify all passes other than the backend, only the generic ops will be supported. All combinations (-uu,-us,...) that actually require different behaviors will need to look at the type of the operands.
+We decided to make a resolve&check pass that is separate from lowering, and is done immediately after parsing the file. This will do all the type inference. By making this pass available, the backends can
+   guarantee the in-memory AST will have types and be type-checked.
+
+Assignment - expanding?
+We didn't discuss this, but my hunch is we should make it loose in that it allows connections of a smaller width expression to a larger width expression
+
+
+
+
 The design of the primitive operations follows the following principles:
 (1) if operand types are known (i.e. FIRRTL front-end), primops whose return type is statically known (no future type introspection needed) are available
 (2) if operand types are not known (i.e. hand-writing FIRRTL pass), generic primops can be used, and a future pass will perform type introspection to replace the generic with the specific primop
@@ -36,15 +61,21 @@ div
    divus(a,b) -> s,a.w+1 ; if divide by -1 
    divsu(a,b) -> s,a.w   ; if divide by 1
    divss(a,b) -> s,a.w+1 ; if divide by -1
-   
+
+quo
+   quouu -> u, a.w
+   quous -> s, a.w + 1
+   quosu -> s, a.w
+   quoss -> u, a.w + 1
+
 mod
    moduu(a,d) -> u,d.w
-   modus(a,d) -> u,d.w-1
+   modus(a,d) -> u,d.w
    modsu(a,d) -> u,d.w
-   modss(a,d) -> u,d.w-1
+   modss(a,d) -> u,d.w
    
 rem
-   remuu(a,b) -> u,min(a.w,b.w) ; 15 % 16 = 15. All remainders must be less than b or a.
+   remuu(a,b) -> u,b.w ; 15 % 16 = 15. All remainders must be less than b or a.
    remus(a,b) -> u,b.w          ; -1 % 32 = 31. Remainder can be larger than abs(a), but not larger than b.
    remsu(a,b) -> s,b.w          ; 1 % -32 = -31. abs(rem) can be larger than abs(a), but not larger than abs(b). 
    remss(a,b) -> s,b.w          ; strictly superset of us and su.