Finished expand-whens. Removed letrec also, a while ago

1 files changed, 9 insertions, 2 deletions

diff --git a/notes/notes.03.18.15.txt b/notes/notes.03.18.15.txt
index f9acf7f5..6b85ccd9 100644
--- a/notes/notes.03.18.15.txt
+++ b/notes/notes.03.18.15.txt
@@ -45,7 +45,10 @@ if w is a wire:
 merge {r=>x, w=>y} with {r=>x} under p : {r=>svmux(p,x,x), w=>y}
 
 if s is a reg:
-merge {r=>x,s=>y} with {r=>x} under p : {r=>svmux(p,x,x), s=>svmux(p,y,void)} ;this is to correctly calculate the ENABLE signal! when actually calculating the input, we will reduce it
+merge {r=>x,s=>y} with {r=>x} under p : {r=>svmux(p,x,x), s=>svmux(p,y,void)} 
+;this is to correctly calculate the ENABLE signal! when actually calculating the input, we will reduce it
+;actually, since we will be doing the reducing anyways, we might as well not do anything different for wires, 
+;  and instead do the reduction step separately
 
 wire r     {r=>VOID}
 r := x     {r=>x}
@@ -53,13 +56,17 @@ when p     {r=>x}
   reg s    {r=>x,s=>VOID}
   s := y   {r=>x,s=>y}
   wire w   {r=>x,s=>y,w=>VOID}
+else       {r=>x}
+  reg s    {r=>x,s=>VOID}
+  wire w   {r=>x,s=>VOID,w=>VOID}
+  w := z   {r=>x,s=>VOID,w=>z}
   w := y   {r=>x,s=>y,w=>y}
 else 
   emptystmt {r=>x}
 ;merge table-c with table-a
 ;get unique keys of table-a + table-c
 ; (r,s,w)
-{r=>(p?x:x),s=>
+{r=>(p?x:x),s=>(p?y:VOID),w=>(p?y:VOID)}