diff options
| author | JADE KIM | 2020-11-18 04:29:01 +0900 |
|---|---|---|
| committer | GitHub | 2020-11-17 19:29:01 +0000 |
| commit | d645921b4ec432e5554863959c3a0cabe5e9a72d (patch) | |
| tree | 1602bbd9cf82347a2b85ff361a34e49845c79d27 /fuzzer | |
| parent | 4dd45a8ea9fdd5bae258d74ac54fcd5744003ac8 (diff) | |
Fix Type Error fuzzer Example code (#1960)
Seq[(Int, DoPrimGen)] to Map[ExprGen[_ <: Expression], Int]
Diffstat (limited to 'fuzzer')
| -rw-r--r-- | fuzzer/src/test/scala/Example.scala | 60 |
1 files changed, 30 insertions, 30 deletions
diff --git a/fuzzer/src/test/scala/Example.scala b/fuzzer/src/test/scala/Example.scala index 89fd19cf..8edb1d55 100644 --- a/fuzzer/src/test/scala/Example.scala +++ b/fuzzer/src/test/scala/Example.scala @@ -14,36 +14,36 @@ object FirrtlCompileProperties extends Properties("FirrtlCompile") { val params = ExprGenParams( maxDepth = size / 3, maxWidth = math.min(size + 1, CheckWidths.MaxWidth), - generators = Seq( - 1 -> AddDoPrimGen, - 1 -> SubDoPrimGen, - 1 -> MulDoPrimGen, - 1 -> DivDoPrimGen, - 1 -> LtDoPrimGen, - 1 -> LeqDoPrimGen, - 1 -> GtDoPrimGen, - 1 -> GeqDoPrimGen, - 1 -> EqDoPrimGen, - 1 -> NeqDoPrimGen, - 1 -> PadDoPrimGen, - 1 -> ShlDoPrimGen, - 1 -> ShrDoPrimGen, - 1 -> DshlDoPrimGen, - 1 -> CvtDoPrimGen, - 1 -> NegDoPrimGen, - 1 -> NotDoPrimGen, - 1 -> AndDoPrimGen, - 1 -> OrDoPrimGen, - 1 -> XorDoPrimGen, - 1 -> AndrDoPrimGen, - 1 -> OrrDoPrimGen, - 1 -> XorrDoPrimGen, - 1 -> CatDoPrimGen, - 1 -> BitsDoPrimGen, - 1 -> HeadDoPrimGen, - 1 -> TailDoPrimGen, - 1 -> AsUIntDoPrimGen, - 1 -> AsSIntDoPrimGen, + generators = Map( + AddDoPrimGen -> 1, + SubDoPrimGen -> 1, + MulDoPrimGen -> 1, + DivDoPrimGen -> 1, + LtDoPrimGen -> 1, + LeqDoPrimGen -> 1, + GtDoPrimGen -> 1, + GeqDoPrimGen -> 1, + EqDoPrimGen -> 1, + NeqDoPrimGen -> 1, + PadDoPrimGen -> 1, + ShlDoPrimGen -> 1, + ShrDoPrimGen -> 1, + DshlDoPrimGen -> 1, + CvtDoPrimGen -> 1, + NegDoPrimGen -> 1, + NotDoPrimGen -> 1, + AndDoPrimGen -> 1, + OrDoPrimGen -> 1, + XorDoPrimGen -> 1, + AndrDoPrimGen -> 1, + OrrDoPrimGen -> 1, + XorrDoPrimGen -> 1, + CatDoPrimGen -> 1, + BitsDoPrimGen -> 1, + HeadDoPrimGen -> 1, + TailDoPrimGen -> 1, + AsUIntDoPrimGen -> 1, + AsSIntDoPrimGen -> 1, ) ) params.generateSingleExprCircuit[Gen]() |